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Highlights

Our paper has been accepted for publication in “DSD2022”
Title: “Inference Time Reduction of Deep Neural Networks on Embedded Devices: A Case Study”, DSD 2022. [PDF]

Our paper has been accepted for publication in “GPGPU 2022”,  
Title: “Near LLC Versus Near Main Memory Processing” [PDF]

Patent Applications

* A system and method for training a federated learning model using network data, PCT/SE2022/050506 (Filed)
* Evaluating target domain machine learning model for deployment, PCT/EP2022/063206 (Filed)
* Assembling a multi-purpose dataset, PCT/EP2022/055012 (Filed)
* Source selection using quality of model weights, PCT/EP2022/054120 (Filed)
* Source selection based on diversity for machine learning, PCT/SE2021/050898 (Filed)
* Enabling collaborative learning between heterogenous components, PCT/EP2021/061245 (Filed)

Journals

* S.M. Nabavinejad, S. Reda, M. Ebrahimi, “Coordinated Batching and DVFS for DNN Inference on GPU Accelerators”, IEEE Transactions on Parallel and Distributed Systems, 2022. [PDF][Link]
* KC Chen, CK Tsai, YS Liao, HB Xu, M Ebrahimi, “A Lego-Based Neural Network Design Methodology With Flexible NoC”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, v. 11, pp. 711-724, 2021. [PDF][Link]
* M.S. Hosseini, M. Ebrahimi, P. Yaghini, N. Bagherzadeh, “Near Volatile and Non-Volatile Memory Processing in 3D Systems”, IEEE Transactions on Emerging Topics in Computing, 2021. [PDF][Link]
* S. M. Nabavinejad, M. Baharloo, K. -C. Chen, M. Palesi, T. Kogel, and M. Ebrahimi, “An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, v. 10, no. 3, pp. 268-282, 2020. [PDF][Link]
* K. C. Chen, M. Ebrahimi, T. Y. W, Y. C. Yang, Y. H. Liao, “A NoC-based simulator for design and evaluation of deep neural networks”, Microprocessors and Microsystems, v. 77, 2020. [PDF][Link]
* G. Sahebi, P. Movahedi, M. Ebrahimi, T. Pahikkala, J. Plosila, H. Tenhunen, “GeFeS: A generalized wrapper feature selection approach for optimizing classification performance”, Computers in Biology and Medicine, v. 125, 2020. [PDF][Link]
* L. Huang, C. Yuan, J. Wang, M. Ebrahimi, X. Xie and Q. Li, “ECDR2: Error Corrector and Detector Relocation Router for Network-on-Chip”, IEEE Transactions on Computers, 2020. [PDF][Link]
* M. Baharloo, A. Khonsari, M. Dolati, P. Shiri, M. Ebrahimi, D. Rahmati, “Traffic-aware performance optimization in Real-time wireless network on chip”, Nano Communication Networks, v. 26, 2020. [PDF][Link]
* S. Jiang, Q. Wu, S. Chen, J. Zhan, J. Wang, M. Ebrahimi, and L. Huang, “Testing aware dynamic mapping for path-centric network-on-chip test”, Journal of Integration, v. 67, pp. 134-143, 2019. [PDF][Link]
* J Wang, M Ebrahimi, L Huang, X Xie, Q Li, G Li, A Jantsch, “Efficient Design-for-Test Approach for Networks-on-Chip”, IEEE Transactions on Computers, v. 68, pp. 198-213, 2019. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, “A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks”, IEEE Micro 38 (3), pp. 79-85, 2018. [PDF][Link]
* A. Charif, A. Coelho, M. Ebrahimi, N. Bagherzadeh, NE. Zergainoh, “First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip”, IEEE Transactions on Computers, v. 67, no. 10, pp. 1430-1444, 2018. [PDF][Link]
* R. Salamat, M. Khayambashi, M. Ebrahimi, N. Bagherzadeh, “LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-theory Based Analytical Verification”, IEEE Transactions on Computers, 2018. [PDF][Link]
* J. Wang, M. Ebrahimi, L. Huang, G. Li, and A. Jantsch, “Minimizing the System Impact of Router Faults by Means of Reconfiguration and Adaptive Routing”, Journal of Microprocessors and Microsystems, Vol. 51, Issue. 1, pp. 252-263, 2017. [PDF][Link]
* L. Huang, X. Zhang, M. Ebrahimi, G. Li, “Tolerating transient illegal turn faults in NoCs”, Journal of Microprocessors and Microsystems, Vol. 43, Issue. 1, pp. 104-115, 2016. [PDF][Link]
* R. Salamat, M. Khayambashi, N. Bagherzadeh, and M. Ebrahimi, “A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs”, IEEE Transaction on Computers (IEEE TC), pp. 3265-3279, 2016. [PDF][Link]
* L. Huang, J. Wang, M. Ebrahimi, M. Daneshtalab, X. Zhang, G. Li, and A. Jantsch, “Non-blocking Testing for Network-on-Chip”, IEEE Transaction on Computers (IEEE TC), I. 99, 2pp. 679-692, 2016. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, “A Light-weight Fault-Tolerant Routing Algorithm Tolerating Faulty Links and Routers”, Springer journal on computing, pp. 631-648, 2015. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, S. Dytckov, J. Plosila, “In-Order Delivery Approach for 2D and 3D NoCs”, Journal of Supercomputing, 71(8), pp. 2877-2899, 2015. [PDF][Link]
* F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, “Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs”, Journal of Microprocessors and Microsystems, Vol. 38, Issue. 1, pp. 64-75, 2014. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, J. Flich, and H. Tenhunen, “Path-based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing”, IEEE Transaction on Computers (IEEE TC), Special issue on NOCS, ISBN: 0018-9340, pp. 718-733, 2014. [PDF][Link]
* F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, “Adaptive Load Balancing in Learning-based Approaches for many-core embedded systems”, Journal of Supercomputing, pp. 1214-1234, 2014. [PDF][Link]
* M. Ebrahimi, “Fully adaptive routing algorithms and region-based  approaches for two-dimensional and threedimensional networks-on-chip”, IET Computers and Digital Techniques, Vol. 7, Issue. 6, pp. 264-273, 2013. [PDF][Link]
* M. Ebrahimi, H. Tenhunen, M. Dehyadegari, “Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip”, Journal of Systems Architecture, Vol. 59, Issue. 7, pp 516-527, 2013. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, “Cluster-based Topologies for 3D Networks-on-Chip Using Advanced Inter-layer Bus Architecture”, Journal of Computer and System Sciences, 79(4), pp. 475-491, 2013. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “A systematic reordering mechanism for on-chip networks using efficient congestion-aware method”, Elsevier Journal of Systems Architecture (JSA-Elsevier), pp.213-222, 2013. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “Memory-Efficient On-Chip Network with Adaptive Interfaces”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (IEEE-TCAD), Vol. 31, No. 1, ISBN: 0278-0070, pp. 146-159, 2012. [PDF][Link]
* M. Daneshtalab, M. Kamali, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, and J. Plosila, “Adaptive Input-output Selection Based On-Chip Router Architecture”, Journal of Low Power Electronics (JOLPE) Vol. 8, No. 1, pp. 11-29, 2012. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, T. C. Xu, P. Liljeberg, and H. Tenhunen, “A generic adaptive path-based routing method for MPSoCs”, Journal of Systems Architecture (JSA-elsevier), Vol. 57, No. 1, pp. 109-120, ISBN: 1383-7621, 2011. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, “Low distance path-based multicast algorithm for Network-on-Chips”, IET (IEE) Special issue on NoC, Vol. 3, Issue 5, pp. 430-442, ISBN: 1751-8601, 2009. [PDF][Link]

Conference Papers

* H. Bitalebi, V. Geraeinejad, M. Ebrahimi, “Near LLC Versus Near Main Memory Processing”, pp.1-6, GPGPU 2022. [PDF][Link]
* Isma-Ilou Sadou, S.M. Nabavinejad, Z. Lu, M. Ebrahimi, “Inference Time Reduction of Deep Neural Networks on Embedded Devices: A Case Study”, DSD 2022. [PDF][Link]
* J. Taghia, F. Moradi, H. Larsson and X. Lan, M. Ebrahimi, A. Johnsson, “Policy-Induced Unsupervised Feature Selection: A Networking Case Study”, IEEE INFOCOM, pp. 750-759, 2022. [PDF][Link]
* J. Taghia, F. Moradi, H. Larsson, X. Lan, M. Ebrahimi, A. Johnsson, “Demonstration of Policy-Induced Unsupervised Feature Selection in a 5G network”, IEEE INFOCOM, pp. 1-2, 2022. [PDF][Link]
* F. G. Sanz, M. Ebrahimi, A. Johnsson, “Exploring Approaches for Heterogeneous Transfer Learning in Dynamic Networks”, NOMS 2022-2022 IEEE/IFIP Network Operations and Management Symposium, 2022, pp. 1-9. [PDF][Link]
* N. Rohbani, M. Ebrahimi, “SRAM gauge: SRAM health monitoring via cells race”, IEEE/ACM International Symposium on Low Power Electronics and Design, pp.1-6, 2021. [PDF][Link]
* E. Malekzadeh, N. Rohbani, Z. Lu, M. Ebrahimi, “The Impact of Faults on DNNs: A Case Study”, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp.1-6, 2021. [PDF][Link]
* F. G. Sanz, M. Ebrahimi, A. Johnsson, “On Heterogeneous Transfer Learning for Improved Network Service Performance Prediction”, IEEE Global Communications Conference (GLOBECOM), pp. 1-6, 2021. [PDF][Link]
* M. Karami, M. H. Haghbayan, M. E., A. Miele, H. Tenhunen, J. Plosila, “Hierarchical Fault Simulation of Deep NeuralNetworks on Multi-Core Systems”, In Proc. of European Test Symposium (ETS), 2021. [PDF][Link]
* M. S. Hosseini, M. Ebrahimi, P. Yaghini, and N. Bagherzadeh, “Application Characterization for Near Memory  Processing”, In Proc. of 29th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), 2021. [PDF][Link]
[5] M. Abdollahi, M. Baharloo, F. Shokouhinia, M. Ebrahimi, “RAP-NoC: Reliability Assessment of Photonic Network-on-Chips, A simulator”, Proceedings of the Eight Annual ACM International Conference on Nanoscale Computing and Communication, pp. 1-7, 2021. [PDF][Link]
* M. Karami, M. H. Haghbayan, M. Ebrahimi, H. Nejatollahiz,  H. Tenhunen, and J. Plosila, “High-Performance Parallel Fault Simulation for Multi-Core Systems”, In Proc. of 29th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), 2021.  [PDF][Link]
* S. M. Nabavinejad, S. Reda, and M. Ebrahimi, “BatchSizer: Power-Performance Trade-off for DNN Inference”, In Proc. of Asia and South Pacific Design Automation Conference (ASPDAC), pp. 819–824, 2020. [PDF][Link]
* KCJ Chen, M Ebrahimi, TY Wang, YC Yang, “NoC-based DNN Accelerator: A Future Design Paradigm”, International Symposium on Networks-on-Chip, pp. 1-8, 2019. [PDF][Link]
* J. Zhan, L. Huang, J. Wang, M. Ebrahimi and Q. Li, “Online Path-Based Test Method for Network-on-Chip”, In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, pp. 1-5, 2019. [PDF][Link]
* L. Huang, S. Chen, Q. Wu, M. Ebrahimi, J. Wang, S. Jiang, Q. Li, “A Lifetime-aware Mapping Algorithm to Extend MTTF of Network-on-Chips”, in Proc. of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), PP. 147-152, 2018. [PDF][Link]
* S. Jiang, Q. Wu, S. Chen, J. Wang, M. Ebrahimi, L. Huang, Q. Li, “Optimizing Dynamic Mapping Techniques for On-Line NoC Test”, in Proc. of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), PP. 227-232, 2018. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, “EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks”, in proc. of International Symposium on Computer Architecture (ISCA), pp. 703-715, 2017. [PDF][Link]
* M. Ebrahimi, A. Y. Weldezion and M. Daneshtalab, “NoD: Network-on-Die as a Standalone NoC for Heterogeneous Many-core Systems in 2.5D ICs”, in proc. of 19th CSI International Symposium on Computer Architecture & Digital Systems (CADS), pp. 1-6, 2017. [PDF][Link]
* G. Sahebi, A. Majd, M. Ebrahimi, J. Plosila, H. Tenhunen, “A Reliable Weighted Feature Selection for Auto Medical Diagnosis”, in Proc. of IEEE International Conference on Industrial Informatics (INDIN), pp. 985-991, 2017. [PDF][Link]
* J. Wang, M. Ebrahimi, L. Huang, Q. Li, G. Li , A. Jantsch, “Non-Blocking BIST for Continuous Reliability Monitoring of Networks-on-Chip”, in Proc. of IEEE International Symposium on Circuits & Systems (ISCAS), pp- 1-4, 2017. [PDF][Link]
* R. Salamat, M. Ebrahimi, N. Bagherzadeh, F. Verbeek, “CoBRA: Low Cost Compensation of TSV failures in 3D-NoC”, 29th edition of the Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 115-120, 2016. [PDF][Link]
* G. Sahebi, A. Majd, M. Ebrahimi, J. Plosila, J. Karimpour, H. Tenhunen “SEECC: A Secure and Efficient Elliptic Curve Cryptosystem for E-health Applications”, The International Conference on High Performance Computing & Simulation (HPCS), pp. 492-500, 2016. [PDF][Link]
* J. Wang, Y. Huang, M. Ebrahimi, L. Huang, Q. Li, A. Jantsch, and G. Li, “VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping”, in Proc. of ACM international workshop on Many-core Embedded Systems (NoCArC), pp. 18-25, 2016. [PDF][Link]
* X. Zhang, M. Ebrahimi, L. Huang, G. Li, “Fault-Resilient Routing Unit in NoCs”, in IEEE international conference on System-on-Chip, (SoCC), pp. 164-169, 2015. [PDF][Link]
* A. Weldezion, M. Ebrahimi, M. Daneshtalab and H. Tenhunen, “Automated Power and Latency Management in Heterogeneous 3D NoCs”, in Proc. of ACM international workshop on Many-core Embedded Systems (NoCArC), PP. 33-38, 2015. [PDF][Link]
* J. Wang, M. Ebrahimi, L. Huang, A. Jantsch, G. Li, “Design of Fault-Tolerant and Reliable Networks-on-Chip”, in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 545-550, 2015. [PDF][Link]
* N. Gupta, M. Kumar, A. Sharma, M. S. Gaur, V. Laxmi, M. Daneshtalab, M. Ebrahimi, “Improved Route Selection Approaches using Q-learning framework for 2D NoCs”, in Proceedings of 3rd ACM International Workshop on Many-core Embedded Systems, (MES), pp. 33-40, 2015. [PDF][Link]
* A. Rezaei, M. Daneshtalab, D. Zhao, F. Safaei, X. Wang, M. Ebrahimi, “Dynamic Application Mapping Algorithm for Wireless Network-on-Chip”, in Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), pp. 421-424, 2015. [PDF][Link]
* X. Zhang, M. Ebrahimi, L. Huang, G. Li, and A. Jantsch, “A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs”, in Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 365-369, 2015. [PDF][Link]
* R. Salamat, M. Ebrahimi, N. Bagherzadeh, “An Adpative, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on Chip”, in Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 392-395, 2015. [PDF][Link]
* M. Ebrahimi, R. Salamat, N. Bagherzadeh, M. Daneshtalab, “A Fault Resilient Routing Algorithm for sparsely connected 3D NoCs”, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN) in conjunction with DATE, pp. 17-20, 2015. [PDF][Link]
* R. Alizadeh, M. Saneei, and M. Ebrahimi, “Fault-Tolerant Circular Routing Algorithm for 3D-NoC”, in Proceedings of International Congress on Technology, Communication and Knowledge (ICTCK), pp. 1-7, 2014. [PDF][Link]
* M. Ebrahimi, J. Wang, L. Huang, M. Daneshtalab, and A. Jantsch, “Rescuing Healthy Cores Against Disabled Routers”, in Proceedings of the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 98-103, 2014. [PDF][Link]
* M. Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, M. Ebrahimi, and M. Zwolinski, “Fault tolerant and highly adaptive routing for 2D NoCs”, in Proceedings of the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 104-109, 2014. [PDF][Link]
* S. Dytckov, M. Daneshtalab, M. Ebrahimi, H. Anwar, J. Plosila, and H. Tenhunen, “Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks”, in Proceedings of 17th IEEE Euromicro Conference on Digital System Design (DSD), pp. 496-503, 2014. [PDF][Link]
* H. Anwar, M. Daneshtalab, M. Ebrahimi, J. Plosila, H. Tenhunen, S. dytckov, G. Beltrame, “Parameterized AES-based Crypto Processor for FPGAs”, in Proceedings of 17th IEEE Euromicro Conference on Digital System Design (DSD), pp. 465-472, 2014. [PDF][Link]
* H. Anwar, S. Jafri, S. Dytckov, M. Daneshtalab, M. Ebrahimi, A. Hemani, J. Plosila, H. Tenhunen, G.i Beltrame, “Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures”, in Proceedings of 17th IEEE Euromicro Conference on Digital System Design (DSD), pp. 64-68, 2014. [PDF][Link]
* H. Anwar, M. Daneshtalab, M. Ebrahimi, M. Ramírez, J. Plosila, H. Tenhunen, “Integration of AES on Heterogeneous Many-Core system”, in Proceedings of 22nd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 424-427, 2014. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg and H. Tenhunen, “Fault-tolerant Method with Distributed Monitoring and Management Technique for 3D stacked mesh”, in Proceedings of 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS), pp. 87-92, 2013. [PDF][Link]
* H. Anwar, M. Daneshtalab, M. Ebrahimi, J. Plosila and H. Tenhunen, “FPGA implementation of AES-based crypto processor”, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), pp. 369-372, 2013. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab and J. Plosila, “In-Order Delivery Approach for 3D NoCs”, in Proceedings of 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS), pp. 93-98, 2013. [PDF][Link]
* J. Carabaño, F. Dios, M. Daneshtalab, and M. Ebrahimi, “An Exploration of Heterogeneous Systems”, in Proceedings of 8th IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp.1-7, 2013. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, J. Plosila, “Minimal-Path Fault-Tolerant Approach Using Connection-Retaining Structure in Networks-on-Chip”, in Proceedings of 7th International Symposium on Networks-on-Chip (NOCS), pp. 1-8, 2013. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, J. Plosila, H. Tenhunen, “CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems”, in Proceedings of 16th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 1048-1051, 2013. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, J. Plosila, “Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy”, in Proceedings of 16th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 1601-1604, 2013. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, J. Plosila, “High Performance Fault-Tolerant Routing Algorithm for NoC-based Many-Core Systems”, in Proceedings of 21th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 462-469, 2013. [PDF][Link]
* M. Ebrahimi, X. Chang, M. Daneshtalab, J. Plosila, P. Liljeberg, H. Tenhunen, “DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs”, in Proceedings of 21th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 499-503, 2013. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, J. Plosila, F. Mehdipour, “MD: Minimal path-based Fault-Tolerant Routing in On-Chip Networks”, in Proc. of 18th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 35-40, 2013. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, “MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip”, in Proceedings of 15th IEEE Euromicro Conference on Digital System Design (DSD), pp. 201-206, 2012. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, J. Plosila, “GLB - Efficient Global Load Balancing Method for Moderating Congestion in On-Chip Networks”, in Proceedings. of 7th IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-5, 2012. [PDF][Link]
* F. Farahnakian, M. Ebrahimi, M. Daneshtalab, J. Plosila, P. Liljeberg, “Adaptive Reinforcement Learning Method for Networks-on-Chip”, in Proceedings of 16th IEEE 12th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII), pp. 236-243, 2012. [PDF][Link]
* X. Chang, M. Ebrahimi, M. Daneshtalab, T. Westerlund, J. Plosila, “PARS – An Efficient Congestion-Aware Routing Method for Networks-on-Chip”, in Proceedings of 16th IEEE International Symposium on Computer Architecture and Digital Systems (CADS), pp. 166-171, 2012. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, P. Liljeberg, J. Plosila, M. Palesi, and H. Tenhunen, “HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks”, in Proceedings of 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 19-26, 2012. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, “CATRA- Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks”, in Proceedings of 15th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 320-325, 2012. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, “LEAR – A Low-weight and Highly Adaptive Routing Method for Distributing Congestions in On-Chip Networks”, in Proceedings of 20th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 520-524, 2012. [PDF][Link]
* F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and J. Plosila, “Optimized Q-learning model for distributing traffic in on-Chip Networks”, in Proceedings of 3th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp.1-8, 2012. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, J. Plosila, H. Tenhunen, “Dual Congestion Awareness Scheme in On-Chip Networks”, in Proceedings of 3th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp.1-6, 2012. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, J. Plosila, “HIBS-Novel Inter-layer Bus Structure for Stacked Architectures”, in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, 2011. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “Memory-Efficient Logic Layer Communication Platform for 3D-Stacked Memory-on-Processor Architectures”, in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), pp. 1-8, 2011. [PDF][Link]
* F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and J. Plosila, “Q-learning based Congestion-aware Routing Algorithm for On-Chip Network”, in Proceedings of 2th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp.1-7, 2011. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, “Exploring Congestion-Aware Methods for Distributing Traffic in On-Chip Networks”, in Proceedings of Innovative Computing Technology (INCT) pp. 319-327, 2011. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, “Agent-based On-Chip Network Using Efficient Selection Method”, in Proceedings of 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 284-289, 2011. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “High-Performance On-Chip Network Platform for Memory-on-Processor Architectures”, in Proceedings of IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp.1-6, 2011. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, “Efficient Congestion-Aware Selection Method for On-Chip Networks”, in Proceedings of IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp.1-4, 2011. [PDF][Link]
* M. Dehyadegari, M. Daneshtalab, M. Ebrahimi, J. Plosila, and S. Mohammadi, “An Adaptive Fuzzy Logic-based Routing Algorithm for Networks-on-Chip”, in Proceedings of 13th IEEE/NASA-ESA International Conference on Adaptive Hardware and Systems (AHS), pp. 208-214, 2011. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “Cluster-based Topologies for 3D Stacked Architectures”, in Proceedings of ACM International Conference on Computing Frontiers (CF), 2011. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, “Exploring Partitioning Methods for 3D Networks-on-Chip Utilizing Adaptive Routing Model”, in Proceedings of 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 73-80, 2011. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “CMIT- A Novel Cluster-based Topology for 3D Stacked Architectures”, in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), 2010. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, “Performance Evaluation of Unicast and Multicast Communication in Three-Dimensional Mesh Architectures”, in Proceedings of 15th International Symposium on Computer Architecture & Digital Systems(CADS), IEEE Press, pp.181-182, 2010. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “Pipeline-Based Interlayer Bus Structure for 3D Networks-on-Chip”, in Proceedings of 15th International Symposium on Computer Architecture & Digital Systems(CADS), IEEE Press, pp.41-47, 2010. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “Input-Output Selection Based Router for Networks-on-Chip”, in Proceedings of 9th International Symposium on VLSI (ISVLSI), IEEE Press, pp. 92-97, 2010. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “A Low-Latency and Memory-Efficient On-Chip Network”, in Proceedings of 4th International Symposium on Network-on-Chip (NOCS), IEEE/ACM Press, pp.99-106, 2010. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, “Partitioning Methods for Unicast/Multicast Traffic in 3D NoC Architecture”, in Proceedings of 13th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), IEEE Press, PP. 127-132, 2010. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, “HAMUM – A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs”, in Proceedings of 18th Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), IEEE Press, pp. 525-532, 2010. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, H. Tenhunen, “A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing”, in Proceedings of 18th Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), IEEE Press, pp. 547-550, 2010. [PDF][Link]
* M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, “High-Performance TSV Architecture for 3-D ICs”, in Proceedings of 9th International Symposium on VLSI (ISVLSI), IEEE Press, pp. 467-468, 2010. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, “Performance Analysis of 3D NoCs Partitioning Methods”, in Proceedings of 9th International Symposium on VLSI (ISVLSI), IEEE Press, pp. 467-468, 2010. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, “An Efficient Unicast/Multicast Routing Protocol for MPSoCs”, in Proceedings of 12th Euromicro Conference On Digital System Design (DSD), IEEE Press, pp. 203-206, 2009. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, S. Mohammadi, A. Afzali-Kusha, H. Tenhunen, “An Efficient Dynamic Multicast Routing Protocol for Distributing Traffic in NOCs”, in Proceedings of 12th IEEE/ACM International Conference on Design, Automation, and Test in Europe (DATE), IEEE Press, pp. 1064-1069, 2009. [PDF][Link]
* M. Ebrahimi, M. Daneshtalab, N. Sreejesh, P. Liljeberg, H. Tenhunen, “Efficient Network Interface Architecture for Network-on-Chips”, in Proceedings of 27th Norchip, IEEE Press, pp. 1-4, 2009. [PDF][Link]

Book Chapters

* KCJ Chen, M Ebrahimi, “Routing algorithm design for power-and temperature-aware NoCs”, Advances in Computers, v. 124, 2022. [Link]
* M. Ebrahimi, “Reliable and Adaptive Routing Algorithms for 2D and 3D Networks-on-Chip”, book chapter in Routing Algorithms in Networks-on-Chip (1st ed.), Springer, 2014. [Link]
* M. Ebrahimi, Masoud Daneshtalab, “Learning-based Routing Algorithms for on-Chip Networks”, book chapter in Routing Algorithms in Networks-on-Chip (1st ed.), Springer, 2014. [Link]
* M. Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen, “Path-based Multicast Routing for 2D and 3D Mesh Networks”, book chapter in Routing Algorithms in Networks-on-Chip (1st ed.), Springer 2014. [Link]

Paper in Education

* M. Ebrahimi, A. Kelati, E. Nkonoki, A. Kondoro, D. Rwegasira, I. Ben Dhaou, V. Taajamaa, H. Tenhunen, “Creation of CERID: Challenge, Education, Research, Innovation, and Deployment  In the Context of Smart MicroGrid”, in Proc. of IST-Africa, 2019. [PDF][Link]

Edited Proceedings

* M. Ebrahimi, J. Chen, Proceedings of the 11th International Workshop on Network on Chip Architectures (NoCArc), IEEE 2018, ISBN 978-1-5386-8552-5, Japan, 2018.
* H Sarbazi-Azad, N Bagherzadeh, M Ebrahimi, M Daneshtalab, Introduction to the Special Section on On-chip parallel and network-based systems, 2016.
* M. Ebrahimi, R. Locatelli, Proceedings of the 8th International Workshop on Network on Chip Architectures, NoCArc '15, Waikiki, HI, USA, December 5, 2015. ACM2015, ISBN 978-1-4503-3963-6
* M. Ebrahimi, D. Goehringer, M. Daneshtalab, M. Palesi, S. Sonntag, F. Angiolini (Eds.), Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES), Held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), ISBN 978-1-4503-3408-2, 2015.
* M. Daneshtalab, M. Palesi, F. Angiolini, J. Plosila, M. Ebrahimi, (Eds.), Proceedings of the 2nd International Workshop on Many-core Embedded Systems (MES), Held in conjunction with the 41st Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), ISBN 978-1-4503-2822-7, 2014.

Edited Special Issue of Journal

* K.C. Chen, M. Ebrahimi, M. Palesi, T. Kogel, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2020.
* H. Sarbazi-Azad, N. Bagherzadeh, M. Ebrahimi, M. Daneshtalab (Eds.), Introduction to the Special Section on On-chip parallel and network-based systems. Computers & Electrical Engineering 51, 2016.