List of Publications

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    2018

  • Lightweight Message Authentication for Constrained Devices, (with Mats Näslund, G. Selander, F. Lindqvist), in Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks (WiSec'2018) June 18-20, 2018, Stockholm, Sweden, pp. 196-201.

  • One-Sided Countermeasures for Side-Channel Attacks Can Backfire, (with Y. Yu, F. Marranghello, V. D. Teijeira), in Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks (WiSec'2018) June 18-20, 2018, Stockholm, Sweden, pp. 299-301.

  • An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms, (with M. Teslenko), in Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (HOST'2018) May 6-10, 2018, McLean, VA, USA, pp. 65-72.

  • FPGA Based True Random Number Generators Using Non-Linear Feedback Ring Oscillators, (with S. Tao, Y. Yu), in Proceedings of the 16th IEEE International NEWCAS Conference (NEWCAS'2018) June 24-27, 2018, Montreal, Canada.

  • Comparison of CRC and KECCAK Based Message Authentication for Resource-Constrained Devices, (with S. Tao, Y. Yu), in Proceedings of the 16th IEEE International NEWCAS Conference (NEWCAS'2018) June 24-27, 2018, Montreal, Canada.

  • On Designing PUF-Based TRNGs with Known Answer Tests, (with Y. Yu, M. Näslund, S. Tao), in IEEE Nordic Circuits and Systems Conference (NORCAS) Oct. 30-31, 2018, Tallin, Estonia.

  • A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks, in Proceedings of the IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL'2018) May 16-18, 2018, Linz, Austria, pp. 31-37.

  • Message Authentication Based on Cryptographically Secure CRC without Polynomial Irreducibility Test , (with M. Näslund, G. Selander, F. Lindqvist), Cryptography and Communications - Discrete Structures, Boolean Functions and Sequences, vol. 10, issue 2, 2017, pp. 383-399.

  • Energy-efficient cryptographic primitives, in Facta Universitatis, Series: Electronics and Energetics vol. 31, issue 2, 2018, pp. 157-167.
    2017

  • Reliable Low-Overhead Arbiter-Based Physical Unclonable Functions for Resource-Constrained IoT Devices, (with S. Tao), in Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, January 23-25, 2017, Stockholm, Sweden.

  • Temperature Aware Phase/Frequency Detector-Based RO-PUFs Exploiting Bulk-Controlled Oscillators, (with S. Tao), in Proceedings of Design and Test in Europe (DATE'2017), March 27-31, 2017, Lausanne, Switzerland, pp. 686-691.

  • Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST, (with M. Näslund, G. Carlsson, J. Fornehed, B. Smeets), Journal of Signal Processing Systems, 2017, vol. 87, issue 3, pp. 371-381.

  • TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches, (with S. Tao), in Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL'2017), May 22-24, 2017, Novi Sad, Serbia.

  • MVL-PUFs: Multiple-Valued Logic Physical Unclonable Functions, (with S. Tao), International Journal of Circuit Theory and Applications, 2017, vol. 45, issue 2, pp. 292-304.
    2016

  • Protecting IMSI and User Privacy in 5G Networks, (with K. Norrman, M. Näslund), International Workshop on 5G Security, in Proceedings of 9th EAI International Conference on Mobile Multimedia Communications (MobiMedia 2016), June 18-19, 2016, Xian, China

  • Error-Correcting Message Authentication for 5G, (with M. Näslund, G. Selander, K. Norrman), International Workshop on 5G Security, in Proceedings of 9th EAI International Conference on Mobile Multimedia Communications (MobiMedia 2016), June 18-19, 2016, Xian, China

  • A SAT-Based Algorithm for Finding Short Cycles in Shift Register Based Stream Ciphers, (with M. Teslenko), Cryptology ePrint Archive, Report 2016/1068, Nov. 2016, https://eprint.iacr.org/2016/1068

  • Ultra-energy-efficient temperature-stable physical unclonable function in 65 nm CMOS, (with S. Tao), Electronics Letters vol. 52 (10), pp. 805-806.

  • On Constructing Secure and Hardware-Efficient Invertible Mappings, in Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL'2016), May 18-20, Hokkaido, Japan

  • Physical Unclonable Functions based on Temperature Compensated Ring Oscillators, (with S. Tao), Cryptology ePrint Archive, Report 2016/898, Sept. 2016, https://eprint.iacr.org/2016/898
    2015

  • Lightweight CRC-based Message Authentication, (with M. Näslund, G. Selander, F. Lindqvist), Cryptology ePrint Archive, Report 2015/1138, Nov. 2015, https://eprint.iacr.org/2015/1138.

  • Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST, (with M. Näslund, G. Carlsson, J. Fornehed, B. Smeets), Arxive Report arXiv: 1511.07792, Nov. 2015, http://arxiv.org/abs/1511.07792

  • CRC-Based Message Authentication for 5G Mobile Technology, (with M. Näslund, G. Selander), International Workshop on 5G Security, in Proceedings of 2015 IEEE Trustcom/BigDataSE/ISPA, vol.1, pp.1186-1191, August 21-22, 2015, Helsinki, Finland.

  • A Random Access Procedure Based on Tunable Puzzles, (with M. Näslund, G. Selander, F. Lindqvist), International Workshop on Security and Privacy in Cybermatics, in Proceedings of 2015 IEEE Conference on Communications and Network Security (CNS), Sept. 30, 2015, Fllorence, Italy, availible at http://www.ericsson.com/res/docs/2015/random-access-procedure.pdf.

  • Espresso: A Stream Cipher for 5G Wireless Communication Systems, (with M. Hell), Cryptography and Communications - Discrete Structures, Boolean Functions and Sequences (CCDS), Dec. 2015, DOI 10.1007/s12095-015-0173-2, available at Cryptology ePrint Archive, Report 2015/241, March 2015, https://eprint.iacr.org/2015/241.

  • A Scan Partitioning Algorithm for Reducing Capture Power of Delay-Fault LBIST, (with Nan Li, G. Carlsson), in Proceedings of Design and Test in Europe (DATE'2015), March 10-14, 2015, Grenoble, France.

  • Cryptographically Secure CRC for Lightweight Message Authentication, (with M. Näslund, G. Selander, F. Lindqvist), Cryptology ePrint Archive, Report 2015/035, January 2015, https://eprint.iacr.org/2015/035.

  • Remotely Managed Logic Built-In Self-Test for Secure M2M Communications, (with M. Näslund, G. Carlsson, J. Fornehed, B. Smeets), Cryptology ePrint Archive, Report 2015/185, January 2015, https://eprint.iacr.org/2015/185.

  • Logic BIST: State-of-the-Art and Open Problems, (with N. Li, G. Carlsson, K. Petersen), Arxive Report arXiv: 1503.04628, March 2015, http://arxiv.org/abs/1503.04628

  • A Fast Heuristic Algorithm for Redundancy Removal, (with M. Teslenko), ArXive Report 1503.06632, March 2015, http://arxiv.org/abs/1503.06632.

  • A Linear-Time Algorithm for Finding All Double-Vertex Dominators of a Given Vertex, (with M. Teslenko), ArXive Report 1503.04994, March 2015, http://arxiv.org/abs/1503.04994.
    2014

  • Keyed Logic BIST for Trojan Detection in SoC, (with M. Näslund, G. Carlsson, B. Smeets), in Proceedings of IEEE International Symposium on System-on-Chip (SOC'2014), Oct. 28-29, 2014, Tampere, Finland.

  • An Equivalence-Preserving Transformation of Shift Registers, in Proceedings of Sequences and Their Applications (SETA'2014), eds. K.-U. Schmidt and A. Winterhof, LNCS 8865, 2014, pp. 187-199, availible at Cryptology ePrint Archive, Report 2014/051, January 2014, http://eprint.iacr.org/2014/051.

  • Energy-Efficient Message Authentication for IEEE 802.15.4-Based Wireless Sensor Networks, (with M. Näslund, G. Selander, V. Tsiatsis), in Proceedings of 32nd Nordic Microelectronics Conference NORCHIP (NORCHIP'2014), Oct. 27-28, 2014, Tampere, Finland.

  • Evaluation of Alternative LBIST Flows: A Case Study, (with Nan Li, G. Carlsson), in Proceedings of 32nd Nordic Microelectronics Conference NORCHIP (NORCHIP'2014), Oct. 27-28, 2014, Tampere, Finland.

  • An New Approach to Reliable FSRs Design, (with M. Liu), in Proceedings of 32nd Nordic Microelectronics Conference NORCHIP (NORCHIP'2014), Oct. 27-28, 2014, Tampere, Finland.

  • Area-Efficient High-Coverage LBIST, (with N. Li), Microprocessors and Microsystems, vol. 38, issue 5, pp. 368-374, Springer, July 2014.

  • Secure and Efficient LBIST for Feedback Shift Register-Based Cryptographic Systems, (with M. Näslund, G. Selander), in Proceedings of 19th IEEE European Test Symposium (ETS'2014), May 26-30, 2014, Paderborn, Germany.

  • A Method for Generating Full Cycles by a Composition of NLFSRs, Design, Codes and Cryptography, Springer, 2014, DOI 10.1007/s10623-014-9947-3.

  • An Algorithm for Constructing a Smallest Register with Non-Linear Update Generating a Given Sequence, (with N. Li), in Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL'2014), May 19-21, 2014, Bremen.
    2013

  • Fault-Tolerant Design, Springer, 2013, ISBN 978-1-4614-2112-2.

  • Protecting Ring Oscillator Physical Unclonable Functions against Modelling Attacks, (with S. S. Mansouri), in Proceedings of Information Security and Cryptology (ICISC2013), Seoul, Korea, November, 27-29, 2013.

  • An Improved Hardware Implementation of the Grain-128a Stream Cipher, (with S. S. Mansouri), in Information Security and Cryptology , Lecture Notes in Computer Science vol. 7839, eds. T. Kwon, M.-K. Lee, and D. Kwon, Springer Berlin Heidelberg, 2013, pp. 278-292.

  • A Scalable Method for Constructing Galois NLFSRs with Period 2n-1 using Cross-Join Pairs, IEEE Transactions on Information Theory, vol. 59, issue 1, 2013, pp. 703-709.

  • Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures, (with S. S. Mansouri), Digital Systems Design Conference (DSD'2013), Santander, Spain, September 4-6, 2013.

  • A Faster Shift-Register Alternative to Filter Generators, (with M. Liu), Digital Systems Design Conference (DSD'2013), Santander, Spain, September 4-6, 2013.

  • Embedding of Deterministic Test Data for In-Field Testing, (with N. Li), ArXive Report 1302.6454, Jan 2013, http://arxiv.org/abs/1302.6454.

  • An Algorithm for Constructing a Smallest Register with Non-Linear Update Generating a Given Binary Sequence, (with N. Li), ArXive Report 1306.5596, Jun 2013, http://arxiv.org/abs/1306.5596.

  • An Improved Hardware Implementation of the Quark Hash Function, (with S. S. Mansouri), RFIDSec'2013 , Lecture Notes in Computer Science vol. 8262, eds. M. Hutter, J.-M. Schmidt, Springer-Verlag Berlin Heidelberg, 2013, pp. 113-127.

  • The Robustness of Balanced Boolean Networks, (with M. Liu), in Complex Networks: Studies in Computational Intelligence, Eds. Menezes, R., Evsukoff, A., Gonzalez, M. C., Springer, Berlin/Heidelberg, vol. 424, 2013, pp. 19-30.

  • A BDD-Based Method for LFSR Parellelization with Application to Fast CRC Encoding, (with S. S. Mansouri), Journal of Multiple-Valued Logic and Soft Computing, vol 21, no. 5-6, 2013, pp. 561-575.

  • A Method for Generating Full Cycles by a Composition of NLFSRs, Proceeding of International Workshop on Coding and Cryptography (WCC'2013), 15-19 April 2013, Bergen, Norway.

  • Secure Key Storage Using State Machines, (with N. Li, S. S. Mansouri), Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL'2013), May 21-24, 2013, Toyama, Japan.

  • On-Chip Area-Efficient Binary Sequence Storage, (with N. Li, S. S. Mansouri), Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI'2013), May 2-4, 2013, Paris, France.

  • Design of a Terminal Solution for Integration of In-home Healthcare Devices and Services towards the Internet-of-Things, (with Pang, Z., P., Chen, Q., Zheng, L.), Enterprise Information Systems, 2013, DOI: 10.1080/17517575.2013.776118.
    2012

  • A Method for Generating Full Cycles by a Composition of NLFSRs, Cryptology ePrint Archive, Report 2012/492, August 2012, http://eprint.iacr.org/2012/492.

  • Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-based Bounded Model Checking, (with M. Liu, M. Teslenko), Journal of Multiple-Valued Logic and Soft Computing, vol 19, no. 1-3, 2012, pp. 109-133.

  • Ring Oscillator Physical Unclonable Function with Multi Level Supply Voltages, (with S. S. Mansouri), Proceedings of IEEE International Conference on Computer Design (ICCD'2012), Sept. 30 - Oct. 3, 2012, Montreal, Quebec, Canada.

  • An Architectural Countermeasure against Power Analysis Attacks for FSR-Based Stream Ciphers, (with S. S. Mansouri), in Constructive Side-Channel Analysis and Secure Design, Lecture Notes in Computer Science vol. 7275, eds. W. Schindler and S. Huss, Springer Berlin Heidelberg, pp. 54-68.

  • An Improved Hardware Implementation of the Grain-128a Stream Cipher, (with S. S. Mansouri), in Information Security and Cryptology, Lecture Notes in Computer Science vol. 7839, eds. T. Kwon, M.-K. Lee, and D. Kwon, Springer Berlin Heidelberg, 2012, pp. 278-292.

  • A List of Maximum-Period NLFSRs, Cryptology ePrint Archive, Report 2012/166, March 2012, http://eprint.iacr.org/2012/166.

  • A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding, (with S. S. Mansouri), Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL'2012), Victoria, BC, Canada, May 14-16, 2012, pp. 128 - 133.

  • Power-Security Trade-off in Multi-Level Power Analysis Countermeasures for FSR-Based Stream Ciphers, (with S. S. Mansouri), Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2012), May 20-23, 2012, Seoul, Korea.

    2011

  • A Scalable Method for Constructing Galois NLFSRs with Period 2n-1 using Cross-Join Pairs, Cryptology ePrint Archive, Report 2011/632, November 2011, http://eprint.iacr.org/2011/632.

  • Synthesis of Parallel Binary Machines, Proceedings of International Conference on Computer-Aided Design (ICCAD'2011), November 7-10, 2011, San Jose, CA, USA, pp. 200-206.

  • AIG Rewriting Using 5-Input Cuts, (with N. Li) Proceedings of International Conference on Computer Design (ICCD'2011), October 9 - 12, 2011, Amherst, MA, USA, pp. 429-430

  • Synthesis of Binary Machines, IEEE Transactions on Information Theory, vol. 57, no. 10, 2011, pp. 6890-6893.

  • A SAT-Based Algorithm for Finding Attractors in Synchronous Boolean Networks, (with M. Teslenko), IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol. 8, no. 5, 2011, pp. 1393-1399.

  • Rule-Based Optimization of AND-XOR Expressions, (with D. Knysh), Journal Facta Universitatis, vol. 24, no. 3, December 2011, pp. 437-449.

  • A Countermeasure Against Power Analysis Attacks for FSR-Based Stream Ciphers, (with S. S. Mansouri), Notes of Symmetric Key Encryption Workshop (SKEW'2011), 16 - 17 February 2011 Lyngby, Denmark.

  • Integrated Logic Synthesis Using Simulated Annealing, (with P. Färm, A. Kuehlmann), Proceedings of Great Lakes Symposium on VLSI (GLSVLSI'2011), May 2-4 2011, Lausanne, Switzerland, pp. 407-410.

  • A Countermeasure Against Power Analysis Attacks for FSR-Based Stream Ciphers, (withe S. Mansouri), Proceedings of Great Lakes Symposium on VLSI (GLSVLSI'2011), May 2-4 2011, Lausanne, Switzerland, pp. 235-240.

  • Rule-Based Optimization of AND-XOR Expressions, (with D. Knysh), Notes of 2011 Reed-Muller Workshop (RM'2011), May 25-26, 2011, Tuusula, Finland, pp. 45-49.

  • AIG Rewriting Using 5-Input Cuts, (with N. Li) Notes of 20th International Workshop on Logic and Synthesis (IWLS'2011), June 3 - 5, 2011, San Diego, CA, USA.

  • Synthesis of Parallel Binary Machines, Notes of 20th International Workshop on Logic and Synthesis (IWLS'2011), June 3 - 5, 2011, San Diego, CA, USA.

  • Synthesis of Parallel Binary Machines, ArXive ePrint Technical Report 1009.5802, May 2011, http://arxiv. org/abs/1105.4514.
    2010

  • Synthesis of Binary K-Stage Machnies, ArXive ePrint Technical Report 1009.5802, Sept. 2010, http://arxiv. org/abs/1009.5802.

  • Finding Matching Initial States for Equivalent NLFSRs in the Fibonacci and the Galois Configurations, IEEE Transactions on Information Theory, vol. 56, no. 6, 2010, pp. 2961-2967.

  • An Algorithm for Constructing a Fastest Galois NLFSR Generating a Given Sequence, (with J.-M.,Chabloz, S. Mansouri), Sequences and Their Applications (SETA'2010), Eds. C. Carlet and A. Pott., LNCS 6338, 2010, pp. 41-55.

  • Pulse Latch Based FSRs for Low-Overhead Hardware Implementation of Cryptographic Algorithms, (with S. S. Mansouri), IEEE International Conference of Computer Design (ICCD'2010), Amsterdam, the Netherlands Oct. 3-6, 2010.

  • Pulse Latch Based Implementation of Trivium for RFID Authentication, (with S. S. Mansouri), Notes of 6th Workshop on RFID Security (RFIDSec'2010), Istanbul, Turkey, June 7 - 9, 2010.

  • Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-based Bounded Model Checking, (with M. Teslenko, M. Liu), Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL'2010), Barcelona, Spain, May 26-28, 2010, pp. 144 - 149 (best paper award).

  • Pulse Latch Based FSRs for Low-Overhead Hardware Implementation of Cryptographic Algorithms, (with S. S. Mansouri), Notes of International Workshop in Logic and Synthesis (IWLS'2010), Irvine, CA, USA, June 18-20, 2010.

  • An NLFSR Re-Synthesis Algorithm for Delay Optimization, (with J.-M.,Chabloz, S. Mansouri), Notes of International Workshop in Logic and Synthesis (IWLS'2010), Irvine, CA, USA, June 18-20, 2010.

  • An Improved Hardware Implementation of the Grain Stream Cipher, (with S. S. Mansouri), Proceedings of Euromicro Conference on Digital System Design (DSD'2010), Lille, France, Sept. 1-3, 2010.
    2009

  • A Transformation from the Fibonacci to the Galois NLFSRs, IEEE Transactions on Information Theory, vol. 55, no. 11, 2009, pp. 5263-5271.

  • How to Speed-Up Your NLFSR-Based Stream Cipher, Proceedings of Design and Test in Europe (DATE'2009), April 20-24, 2009, Nice, France, pp. 878-881.

  • Finding Matching Initial States for Equivalent NLFSRs in the Fibonacci and the Galois Configurations, ArXive ePrint Technical Report 0903.3182, March 2009, arXiv:0903.3182.

  • A SAT-Based Algorithm for Computing Attractors in Synchronous Boolean Networks, (with M. Teslenko), ArXive ePrint Technical Report 0901.4448, January 2009, arXiv:0901.4448.
    2008

  • A Computational Scheme Based on Random Boolean Networks, (with M. Teslenko, H. Tenhunen), Transactions on Computational Systems Biology X, Eds. C. Priami et al., LNBI 5410, 2008, pp. 41-58.

  • Self-Organization for Fault-Tolerance, Proceedings of Third International Workshop on Self-Organizing Systems (IWSOS'2008), December 10-12, 2008, Vienna, Austria, Eds. K. A. Hummel and J. Sterbenz, LNCS 5343, 2008, pp. 145-157.

  • Bio-Inspired Fault-Tolerance, Proceedings of IEEE/ACM International Conference on Bio-Inspired Models of Network, Information, and Computing Systems (BIONETICS'2008), November 25-28, 2008, Hyogo, Japan.

  • Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers, (with M. Teslenko, H. Tenhunen), Proceedings of Design, Automation and Test in Europe (DATE'2008), 10-14 March 2008, Munich, Germany, pp. 1286-1291.

  • How to Increase the Throughput of an NLFSR-based Stream Cipher, Extended Abstracts of the Second Workshop on Mathematical Cryptology (WMC'2008), Eds. A. Ibeeas and J. Gutierrez, October 23-25, 2008, Santander, Spain, pp. 86-89.

  • Learning Robustness from Gene Regulatory Networks, Abstract Book of the 9th International Conference on Systems Biology (ICSB'2008), August 22-28, 2008, Gothenburg, Sweden, p. 179.

  • Learning Fault-Tolerance from Nature, Proceedings of International Biennial Baltic Electronics Conference (invited talk), 2008, October 6-8, 2008, Tallinn, Estonia, pp. 51-58.

  • NLFSR Re-Synthesis for High Throughput, Notes of International Workshop on Logic and Synthesis (IWLS'2007), June 4-6, 2008, Lake Tahoe, CA, USA.

  • Synthesis of NLFSR-Based Pseudo-Random Bit Generators for Stream Ciphers, Proceedings of International Symposium on Applied Computing (IADIS'2005), 10-13 April 2008, Algarve, Portugal.

  • An Equivalence Preserving Transformation from the Fibonacci to the Galois NLFSRs, ArXive ePrint Technical Report 0801.4079, January 2008, arXiv:0801.4079.

    2007

  • A Computational Model Based on Random Boolean Networks, (with M. Teslenko, H. Tenhunen), Proceedings of International Conference on Bio-Inspired Models of Network, Information, and Computing Systems (BIONETICS'2007), December 10-13, 2007, Budapest, Hungary.

  • FIREwork: Redundancy Identification and Removal for Large Combinational Circuits, (with M. Teslenko, H. Tenhunen), Notes of International Workshop on Logic and Synthesis (IWLS'2007), May 30 - June 1, 2007, San Diego, CA, USA, pp. 388-396.

  • Evaluation and Comparison of Threshold Logic Gates, (with V. Lirigis), Proceedings of 37th IEEE International Symposium on Multiple-Valued Logic (ISMVL'2007), May 14-16, 2007, Oslo, Norway, pp. 52-56.

  • A Dynamic Network Model for Nanoscale Systems, (with H. Tenhunen), European NanoSystems'2007, December 3-4, 2007, Paris, France.

    2006

  • Integrated Logic Synthesis Using Simulated Annealing, (with P. Färm and A. Kuehlmann), Notes of International Workshop on Logic Synthesis, June 7-9, 2006, Vail, Colorado, USA.

  • Random Multiple-Valued Networks: Theory and Applications, Proceedings of 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL'2006), May 17-20, 2006, Singapore, pp. 27-33.

  • An Efficient Algorithm for Computing Common Double-Vertex Dominators, (with M. Teslenko, H. Tenhunen), Proceedings of International Symposium on Applied Computing (IADIS'2006), February 25-28, 2006, San Sebastian, Spain, pp. 34-42.

  • A Computational Scheme Based on Random Boolean Networks on the Critical Line, (with H. Tenhunen), Proceedings of International Symposium on Applied Computing (IADIS'2006), February 25-28, 2006, San Sebastian, Spain, pp. 273-281.

  • A Polynomial-Time Algorithm for Computing Bound Sets, (with R. Krenz), IEE Proceedings - Circuits, Devices and Systems}, vol. 153, issue 2, April 2006, pp. 179-184.

    2005

  • Kauffman Networks: Analysis and Applications, (with M. Teslenko, A. Martinelli), Proceedings of International Conference on Computer-Aided Design (ICCAD'2005), November 6-10, 2005, San Jose, CA, USA, pp. 479-484.

  • Compositional Properties of Random Boolean Networks, (with M. Teslenko) Physical Review E, vol. 71, issue 2, May 2005, 056116.

  • Bound-set preserving ROBDD variable orderings may not be optimum, (with M. Teslenko, A. Martinelli), IEEE Transactions on Computers, February 2005, vol. 54, no. 2, pp. 236-238.

  • From Living Cells to Fault-Tolerant Systems: Computing Based on Gene Regulatory Networks, Proceedings of Swedish System-on-Chip Conference (SSoCC'05), April 18-19, 2005, Tammsvik, Sweden.

  • Computing Common Double-Vertex Dominators in Circuit Graphs, (with M. Teslenko), Notes of International Workshop on Logic Synthesis, June 8-10, 2005, Lake Arrowhead, CA, USA.

  • Kauffman Networks: From Nature to Electronics, (with M. Teslenko), Notes of International Workshop on Logic Synthesis, June 8-10, 2005, Lake Arrowhead, CA, USA.

  • Modeling Gene Regulatory Systems by Random Boolean Networks, Proceedings of SPIE Bioengineered and Bioinspired Systems II, vol. 5839, June 2005, pp. 56-65.

  • Phylogenetic Networks with Edge-Disjoint Recombination Cycles, Proceedings of SPIE Bioengineered and Bioinspired Systems II, vol. 5839, June 2005, pp. 381-388.

  • Logic Optimization Technique for Molecular Cascades, (with P. Färm, H. Tenhunen), Proceedings of SPIE Nanotechnology II, vol. 5838, June 2005, pp. 95-104.

  • An Efficient Structural Technique for Boolean Decomposition, (with A. Martinelli), Proceedings of SPIE VLSI Circuits and Systems II, vol. 5837, June 2005, pp. 913-918.

  • Computing a Perfect Input Assignment for Probabilistic Verification, (with M. Teslenko, H. Tenhunen), Proceedings of SPIE VLSI Circuits and Systems II, vol. 5837, June 2005, pp. 929-936.

  • An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs, (with M. Teslenko), Proceedings of Design and Test in Europe (DATE'2005), March 7-11, 2005, Munich, Germany, pp. 406-411.

  • Structural Testing Based on Minimum Kernels, Proceedings of Design and Test in Europe (DATE'2005), March 7-11, 2005, Munich, Germany, pp. 1168-1171.

  • Bound Set Selection and Circuit Re-Synthesis for Area/delay Driven Decomposition, (with A. Martinelli), Proceedings of Design and Test in Europe (DATE'2005) March 7-11, 2005, Munich, Germany, pp. 430-431.

  • Linear-Time Algorithm for Computing Minimum Checkpoint Sets for Simulation-Based Verification of HDL Programs, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2004), May 23-26, 2005, Kobe, Japan.

  • Computing Attractors in Complex Dynamic Networks, (with M. Teslenko, H. Tenhunen), Proceedings of International Symposium on Applied Computing (IADIS'2005), February 23-25, 2005, Algarve, Portugal, pp. 535-543.

  • Improved Boolean Function Hashing based on Multiple-Vertex Dominators, (with R. Krenz), Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'2005), January 21-23, 2005. Shanghai, China.

  • A Fast Algorithm for Finding Common Multiple-Vertex Dominators in Circuit Graphs, (with R. Krenz), Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'2005), January 21-23, 2005. Shanghai, China.

  • Logic Optimization Using Rule-Based Randomized Search, (with P. Färm, A. Kuehlmann), Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'2005), January 21-23, 2005. Shanghai, China.

    2004

  • Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth, (with M. Teslenko), Proceedings of International Conference on Computer-Aided Design (ICCAD'2004), November 7-11, 2004, San Jose, CA, USA.

  • LUT FPGA technology mapping for area minimization with optimum depth, (with M. Teslenko), Notes of International Workshop on Logic Synthesis (IWLS'2004), June 2-4, 2004, San Diego, CA, USA, pp. 22-28.

  • Efficient computation and representation of double-vertex dominators in circuit graphs, (with M. Teslenko), Notes of International Workshop on Logic Synthesis (IWLS'2004), June 2-4, 2004, San Diego, CA, USA, pp. 44-50.

  • On relation between non-disjoint decomposition and multiple-vertex dominators, (with M. Teslenko, A. Martinelli), Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2004), May 23-26, 2004, Vancouver, Canada.

  • A polynomial-time algorithm for non-disjoint decomposition of multiple-valued functions, Proceedings of 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL'2004), May 19-21, 2004, Toronto, Canada, pp. 309-315.

  • Disjoint-support Boolean decomposition combining functional and structural methods, (with A. Martinelli, R. Krenz), Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC'2004), January 27-30, 2004. Yokohama, Japan.

  • Trading completeness for capacity using probabilistic techniques, (with R. Krenz), Proceedings of Designing Correct Circuits Workshop (DCC'2004), 27-28 March 2004, Barcelona, Spain.

  • TOP: An algorithm for three-level combinational logic optimization, (with Ellervee, P., Miller, D.M., Muzio, J.C., Sullivan, A. J.), IEE Proceedings - Circuits, Devices and Systems, vol. 5, no. 4, pp. 307-314, August 2004.

  • Probabilistic equivalence checking of multiple-valued functions, (with Sack, H.), Journal of Multiple-Valued Logic and Soft Computing, vol. 10, no. 4, pp. 395-414, 2004.

    2003

  • Boolean decomposition based on cyclic chains, (with Teslenko, M., Karlsson, J.), Proceeding of International Conference on Computer Design (ICCD'2003), October 11-13, 2003, San Jose, CA, pp. 504-510.

  • Probabilistic verification based on function hashing, (with Krenz, R.), Proceedings of of NORCHIP'03, November 2003, Riga, Latvia.

  • Two fault tolerant MIPS processor architectures for NOC applications, (with Mathew, J., Tomas, J. ), Proceedings of of NORCHIP'03, November 2003, Riga, Latvia.

  • Roth-Karp decomposition combining functional and structural techniques, (with A. Martinelli, R. Krenz), Notes of International Workshop on Logic Synthesis, May 2003, pp. 18-23.

  • Fast multi-level logic optimization using local transformations, (with P. Färm), Notes of International Workshop on Logic Synthesis, May 2003, pp. 120-126.

  • Implementation of multiple-valued functions using literal-splitting technique, Proceedings of 33rd IEEE International Symposium on Multiple-Valued Logic, May 2003, pp. 7-11.

  • Fast algorithm for computing spectral transforms of Boolean and multiple-valued functions, (with R. Krenz, A. Kuehlmann), Proceedings of 33rd IEEE International Symposium on Multiple-Valued Logic, May 2003, 334-343.

  • Totally self-checking 1-out-of-n checker with application to the design of fault tolerant FIR filter, (with J. Mathew), Proceedings of the International Workshop on the Applications of the Reed-Muller Expansion in Circuit Design, March 2003.

  • Logic Optimization and Technology Mapping for CAEN, (with Färm, P., Tenhunen, H.), Proceedings of NanoTech´2003, February 2003.

  • Electronic nanotechnology based on non-binary principles, (with J. Mathew, Tenhunen, H.), Proceedings of NanoTech´2003, February 2003.

  • A BDD-based fast heuristic algorithm for disjoint decomposition, (with T. Bengtsson, A. Martinelli), Proceedings of Asia and South Pacific Design Automation Conference, ASP-DAC03, January 2003.

    2002

  • Circuit-based Evaluation of the Arithmetic Transform of Boolean Functions, (with Krenz, R., Kuehlmann, A.), Notes of International Workshop on Logic Synthesis, June 4-7, 2002, New Orleans, Louisiana, pp. 321-327.
      [ PDF/6 pages ]

  • A Fast Heuristic Algorithm for Disjoint Decomposition of Boolean Functions, (with Bengtsson, T., Martinelli, A.), Notes of International Workshop on Logic Synthesis, June 4-7, 2002, New Orleans, Louisiana, pp. 51-57.

  • Technology Mapping for Chemically Assembled Electronic Nanotechnology, (with Färm, P.), Notes of International Workshop on Logic Synthesis, June 4-7, 2002, New Orleans, Louisiana, pp. 121-125.

  • Non-Silicon Non-Binary Computing: Why not?, (with Jamal. Y., Mathew. J.), Proceedings of 1st Workshop on Non-Silicon Computation, February 3, 2002, Boston, USA, pp. 23-29.

  • Composition Trees in Finding Best Variable Orderings for ROBDDs, Proceedings of DATE'2002, March 4-8, 2002, Paris, France.

  • A Conjunctive Canonical Expansion of Multiple-Valued Functions, (with Färm, P.), Proceedings of 32nd International Symposium on Multiple-Valued Logic, May 14-18, 2002, Boston, USA.
      [ PDF/4 pages ]

  • Multiple-Valued Logic Synthesis and Optimization, Logic Synthesis and Verification, Eds.: S. Hassoun and T. Sasao, Kluwer Academic Publishers, 2002, pp. 89-114.

  • On-the-fly proper cut recognition based on circuit graph analysis, (with Krenz, R.), Proceedings of of NORCHIP'02, November 2002, Copenhagen, Denmark.

  • Roth-Karp decomposition of large Boolean functions with application to logic design, (with A. Martinelli, T. Bengtsson, A. J. Sullivan), Proceedings of of NORCHIP'02, November 2002, Copenhagen, Denmark.

  • Totally self-checking 1-out-of-n checker with application to fault tolerant design, (with J. Mathew), Proceedings of of NORCHIP'02, November 2002, Copenhagen, Denmark.

  • Self-checking checker for 1-out-of-n code based on current-mode CMOS logic, (with J. Mathew), Proceedings of Defect and Fault Tolerance in VLSI Systems Conference, DFT2002, Vancouver, Canada, November 2002.

  • Conjunctive decomposition for multiple-valued input binary-valued output functions, (with P. Färm, R. S. Stankovic, and J. T. Astola), Proceedings of International TICSP Workshop on Spectral Methods and Multirate Signal Processing, Toulouse, France, September 2002, pp. 227-234.

    2001

  • Formal Verification Using Probabilistic Techniques, (with Krenz, R.), Proceedings of of NORCHIP'01, November 12-13, 2001, Stockholm, Sweden, pp. 258-264.
      [ PDF/6 pages ]

  • A Sufficient Condition for Detection of XOR-Type Logic, (with Bengtsson, T.), Proceedings of of NORCHIP'01, November 12-13, 2001, Stockholm, Sweden, pp. 271-279.
      [ PDF/8 pages ]

  • Programmable Logic in Fault-Tolerant Design, (with Bengtsson, T., Krenz, R.), Proceedings of 4th Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD'2001), September 11-13, 2001, Laurel, Maryland, USA.

  • An Algorithm for Detecting XOR-Type Logic, (with Bengtsson, T.), Proceedings of 5th International Workshop on the Applications of the Reed-Muller Expansion in Circuit Design, August 10-11, 2001, Starkville, Mississippi, USA, pp. 271-276.
      [ PDF/6 pages ]

  • Minimization of Multiple-Valued Functions in Post Algebra, (with Jiang, Y., Brayton, R.), Proceedings of International Workshop on Logic Synthesis, June 12-15, 2001, Lake Tahoe, California, pp. 132-138.
      [ PDF/6 pages ]

  • A Design Technique for High-Performance Self-Checking Combinational Circuits, Proceedings of IEEE European Test Workshop, May 29 - June 1, 2001, Stockholm, Sweden, pp. 11-13.
      [ PDF/3 pages ]

  • Power Efficient Inter-Mode Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology, (with Ben Dhaou, I., Tenhunen, H.), Proceedings of 31st IEEE International Symposium on Multiple-Valued Logic, May 25-27, 2001, Warsaw, Poland, pp. 61-66.
      [ PDF/6 pages ]

    2000

  • Easily Testable Multiple-Valued Logic Circuits, (with Muzio, J. C.), IEEE Transactions on Computers, 49, 2000, pp. 1285-1289.
      [ PDF/5 pages ]

  • A Comment on "Graph-Based Algorithm for Boolean Function Manipulation", (with Macchiarulo, L.), IEEE Transactions on Computers, 49, 2000, pp. 1290-1292.
      [ PDF/3 pages ]

  • Upper Bound on the Number of Products in a Sum-of-Product Expansion of Multiple-Valued Functions, Multiple-Valued Logic, An International Journal, 5, 2000, pp. 349-364.
      [ PDF/17 pages ]

  • A Sufficient Condition for Detecting AND-OR-AND-Type Logic, (with Millberg, M., Sullivan, A.J.), Proceedings of International Workshop of Logic Synthesis, May 31 - June 2, 2000, Dana Point, CA, pp. 147-151.
      [ PDF/5 pages ]

  • Representation of Multiple-Valued Functions with Mod-p-Decision Diagrams, (with Sack, H., Meinel, C.), Proceedings of International Workshop of Logic Synthesis, May 31 - June 2, 2000, Dana Point, CA, pp. 341-348.
      [ PDF/8 pages ]

  • Probabilistic Verification of Multiple-Valued Functions, (with Sack, H.), Proceedings of 30th IEEE International Symposium on Multiple-Valued Logic, May 23-25, 2000, Portland, Oregon, pp. 460-467.
      [ PDF/7 pages ]

  • Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions, (with Sack, H., Meinel, C.), Proceedings of 30th IEEE International Symposium on Multiple-Valued Logic, May 23-25, 2000, Portland, Oregon, pp. 233-239.
      [ PDF/6 pages ]

  • TOP: An Algorithm for Three-Level Optimization of PLDs, (with Ellervee, P., Miller, D.M., Muzio, J. C.), Proceedings of Design, Automation and Test in Europe Conference and Exhibition, March 28-30, 2000, Paris, France, p. 751 (best poster award).
      [ PDF/1 page ]

    1999

  • Multiple-Valued Logic in VLSI: Challenges and Opportunities, Proceedings of NORCHIP'99 (invited talk), November 8-9, 1999, Oslo, Norway, pp. 340-350.
      [ PDF/10 pages ]

  • A New Decomposition of Boolean Functions, Proceedings of NORCHIP'99, November 8-9, 1999, Oslo, Norway, pp. 310-316.
      [ PDF/6 pages ]

  • Composition of Reduced Ordered Binary Decision Diagrams, Proceedings of International Workshop on Logic Synthesis, June 27-30, 1999, Lake Tahoe, California, pp. 173-176.
      [ PDF/4 pages ]

  • A Fast Algorithm for Three-Level Logic Optimization (with Ellervee, P.), Proceedings of International Workshop on Logic Synthesis, June 27-30, 1999, Lake Tahoe, California, pp. 151-154.
      [ PDF/4 pages ]

  • On Disjoint Covers and ROBDD Size (with Miller, D.M.), Proceedings of 1999 IEEE Pacific Rim Conference on Communications, Computer and Signal Processing, August 23-25, 1999, Victoria, B.C., Canada, pp. 162-164.
      [ PDF/3 pages ]

  • AOXMIN-MV: A Heuristic Algorithm for AND-OR-XOR Minimization (with Miller, D.M., Muzio, J. C.), Proceedings of 4th International Workshop on the Applications of the Reed-Muller Expansion in Circuit Design, August 20-21, 1999, Victoria, B.C., Canada, pp. 37-54.
      [ PDF/17 pages ]

  • Evaluation of m-valued Fixed Polarity Generalizations of Reed-Muller Canonical Form, Proceedings of 29th International Symposium on Multiple-Valued Logic, May 20-22, 1999, Freiburg, Germany, pp. 92-98.
      [ PDF/7 pages ]

    1998

  • The Spectrality Decision Problem (with Muzio, J.C.), International Journal Approximation Theory and Applications, 14:3, 1998, pp. 73-84.

      [ PDF/12 pages ]

  • On Dependable Strategy for Dynamic Reordering Algorithms (with Miller, D.M.), Proceedings of 7th International Workshop on on Post-Binary ULSI Systems, Fukuoka, Japan, May 26, 1998, pp. 46-48.
      [ PDF/2 pages ]

    1997

  • AOXMIN: A Three-Level Heuristic AND-OR-XOR Minimizer for Boolean Functions (with Miller, D.M., Muzio, J.C.), Proceedings of 3rd International Workshop on the Applications of the Reed-Muller Expansion in Circuit Design, Oxford, UK, Sept. 19-20, 1997, pp. 209-218.
      [ PDF/10 pages ]

  • On the Relation Between Disjunctive Decomposition and ROBDD Variable Ordering (with Miller, D.M., Muzio, J.C.), Proceedings of 1997 IEEE Pacific Rim Conference on Communications, Computer and Signal Processing, Victoria, B.C., Canada, August 20-22, 1997, pp. 688-691.

      [ PDF/4 pages ]

  • On the Best ROBDD Variable Ordering for Functions with Disjunctive Decompositions (with Miller, D.M., Muzio, J.C.), IEE Journal of Electronics Letters, 33, 1997, pp. 1198-1200.

      [ PDF/5 pages ]

  • Finding Composition Trees for Multiple-Valued Functions (with Muzio, J.C. and von Stengel, B.), Proceedings of 27th International Symposium on Multiple-Valued Logic, 1997, pp. 19-26.

      [ PDF/8 pages ]

    1996

  • Testability of Generalized Multiple-Valued Reed-Muller Circuits (with Muzio, J.C.), Proceedings of 26th International Symposium on Multiple-Valued Logic, 1996, pp. 56-61.

      [ PDF/6 pages ]

  • Generalized Reed-Muller Canonical Form for a Multiple-Valued Algebra (with Muzio, J.C.), Multiple-Valued Logic, An International Journal, 1, 1996, pp. 65-84.

      [ PDF/21 pages ]

    1995 and before

  • Upper bound on number of products in AND-OR-XOR expansion of logic functions (with Miller, D.M., Muzio, J.C.), IEE Journal of Electronics Letters, 31, 1995, pp. 541-542.

      [ PDF/5 pages ]

  • The Evaluation of Full Sensitivity for Test Generation in MVL Circuits (with Gurov, D.B., Muzio, J.C.), Proceedings of 25th International Symposium on Multiple-Valued Logic, 1995, pp. 104-109.

      [ PDF/5 pages ]

  • Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits (with Gurov, D.B., Muzio, J.C.), Proceedings of 24th International Symposium on Multiple-Valued Logic, 1994, pp. 284-289.

      [ PDF/5 pages ]

  • A Device for Computing of Implicants (with Bondar I.N., Shmerko, V.P., Janushkevich, S.N.), An author's certificate of USSR, No 1686460, G 06 F 15/353, 1991 (in Russian).