List of Publications
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2018
 Lightweight Message Authentication for Constrained Devices, (with
Mats Näslund, G. Selander, F. Lindqvist), in Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks (WiSec'2018) June 1820, 2018, Stockholm, Sweden, pp. 196201.
 OneSided Countermeasures for SideChannel Attacks Can Backfire, (with
Y. Yu, F. Marranghello, V. D. Teijeira), in Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks (WiSec'2018) June 1820, 2018, Stockholm, Sweden, pp. 299301.
 An efficient SATbased algorithm for finding short cycles in cryptographic algorithms, (with
M. Teslenko), in Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (HOST'2018) May 610, 2018, McLean, VA, USA, pp. 6572.
 FPGA Based True Random Number Generators Using NonLinear Feedback Ring Oscillators, (with
S. Tao, Y. Yu), in Proceedings of the 16th IEEE International NEWCAS Conference (NEWCAS'2018) June 2427, 2018, Montreal, Canada.
 Comparison of CRC and KECCAK Based Message Authentication for ResourceConstrained Devices, (with S. Tao, Y. Yu), in Proceedings of the 16th IEEE International NEWCAS Conference (NEWCAS'2018) June 2427, 2018, Montreal, Canada.
 On Designing PUFBased TRNGs with Known Answer Tests, (with
Y. Yu, M. Näslund, S. Tao), in IEEE Nordic Circuits and Systems Conference (NORCAS) Oct. 3031, 2018, Tallin, Estonia.
 A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks, in Proceedings of the IEEE 48th International Symposium on MultipleValued Logic (ISMVL'2018) May 1618, 2018, Linz, Austria, pp. 3137.
 Message Authentication Based on Cryptographically Secure CRC without Polynomial Irreducibility Test
, (with M. Näslund, G. Selander, F. Lindqvist), Cryptography and Communications  Discrete Structures, Boolean Functions and Sequences, vol. 10, issue 2, 2017, pp. 383399.
 Energyefficient cryptographic primitives, in Facta Universitatis, Series: Electronics and Energetics vol. 31, issue 2, 2018, pp. 157167.
2017
 Reliable LowOverhead ArbiterBased Physical Unclonable Functions for ResourceConstrained IoT Devices, (with S. Tao), in Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, January 2325, 2017, Stockholm, Sweden.
 Temperature Aware Phase/Frequency DetectorBased ROPUFs Exploiting BulkControlled Oscillators, (with S. Tao), in Proceedings of Design and Test in Europe (DATE'2017), March 2731, 2017, Lausanne, Switzerland, pp. 686691.
 Two Countermeasures Against Hardware Trojans Exploiting NonZero Aliasing Probability of BIST, (with M. Näslund, G. Carlsson, J. Fornehed, B. Smeets), Journal of Signal Processing Systems, 2017, vol. 87, issue 3, pp. 371381.
 TVLTRNG: SubMicrowatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches, (with S. Tao),
in Proceedings of IEEE International Symposium on MultipleValued Logic (ISMVL'2017), May 2224, 2017, Novi Sad, Serbia.
 MVLPUFs: MultipleValued Logic Physical Unclonable Functions, (with S. Tao), International Journal of Circuit Theory and Applications, 2017, vol. 45, issue 2, pp. 292304.
2016
 Protecting IMSI and User Privacy in 5G Networks, (with K. Norrman, M. Näslund),
International Workshop on 5G Security, in Proceedings of 9th EAI International Conference on Mobile Multimedia Communications (MobiMedia 2016), June 1819, 2016, Xian, China
 ErrorCorrecting Message Authentication for 5G, (with M. Näslund, G. Selander, K. Norrman),
International Workshop on 5G Security, in Proceedings of 9th EAI International Conference on Mobile Multimedia Communications (MobiMedia 2016), June 1819, 2016, Xian, China
 A SATBased Algorithm for Finding Short Cycles in Shift Register Based Stream Ciphers, (with M. Teslenko), Cryptology ePrint Archive, Report 2016/1068, Nov. 2016, https://eprint.iacr.org/2016/1068
 Ultraenergyefficient temperaturestable physical unclonable function in 65 nm CMOS, (with S. Tao), Electronics Letters vol. 52 (10), pp. 805806.
 On Constructing Secure and HardwareEfficient Invertible Mappings,
in Proceedings of IEEE International Symposium on MultipleValued Logic (ISMVL'2016), May 1820, Hokkaido, Japan
 Physical Unclonable Functions based on Temperature Compensated Ring Oscillators, (with S. Tao), Cryptology ePrint Archive, Report 2016/898, Sept. 2016, https://eprint.iacr.org/2016/898
2015
 Lightweight CRCbased Message Authentication, (with M. Näslund, G. Selander, F. Lindqvist), Cryptology ePrint Archive, Report 2015/1138, Nov. 2015, https://eprint.iacr.org/2015/1138.
 Two Countermeasures Against Hardware Trojans Exploiting NonZero Aliasing Probability of BIST, (with M. Näslund, G. Carlsson, J. Fornehed, B. Smeets), Arxive Report arXiv: 1511.07792, Nov. 2015, http://arxiv.org/abs/1511.07792

CRCBased Message Authentication for 5G Mobile Technology, (with M. Näslund, G. Selander), International Workshop on 5G Security, in Proceedings of 2015 IEEE Trustcom/BigDataSE/ISPA, vol.1, pp.11861191, August 2122, 2015, Helsinki, Finland.

A Random Access Procedure Based on Tunable Puzzles, (with M. Näslund, G. Selander, F. Lindqvist), International Workshop on Security and Privacy in Cybermatics, in Proceedings of 2015 IEEE Conference on Communications and Network Security (CNS), Sept. 30, 2015, Fllorence, Italy, availible at http://www.ericsson.com/res/docs/2015/randomaccessprocedure.pdf.
 Espresso: A Stream Cipher for 5G Wireless Communication Systems, (with M. Hell), Cryptography and Communications  Discrete Structures, Boolean Functions and Sequences (CCDS), Dec. 2015, DOI 10.1007/s1209501501732, available at Cryptology ePrint Archive, Report 2015/241, March 2015, https://eprint.iacr.org/2015/241.

A Scan Partitioning Algorithm for Reducing Capture Power of DelayFault LBIST, (with Nan Li, G. Carlsson), in Proceedings of Design and Test in Europe (DATE'2015), March 1014, 2015, Grenoble, France.
 Cryptographically Secure CRC for Lightweight Message Authentication, (with M. Näslund, G. Selander, F. Lindqvist), Cryptology ePrint Archive, Report 2015/035, January 2015, https://eprint.iacr.org/2015/035.
 Remotely Managed Logic BuiltIn SelfTest for Secure M2M Communications, (with M. Näslund, G. Carlsson, J. Fornehed, B. Smeets), Cryptology ePrint Archive, Report 2015/185, January 2015, https://eprint.iacr.org/2015/185.
 Logic BIST: StateoftheArt and Open Problems, (with N. Li, G. Carlsson, K. Petersen), Arxive Report arXiv: 1503.04628, March 2015, http://arxiv.org/abs/1503.04628
 A Fast Heuristic Algorithm for Redundancy Removal, (with M. Teslenko),
ArXive Report 1503.06632, March 2015, http://arxiv.org/abs/1503.06632.
 A LinearTime Algorithm for Finding All DoubleVertex Dominators of a Given Vertex, (with M. Teslenko),
ArXive Report 1503.04994, March 2015, http://arxiv.org/abs/1503.04994.
2014

Keyed Logic BIST for Trojan Detection in SoC, (with M. Näslund, G. Carlsson, B. Smeets), in Proceedings of
IEEE International Symposium on SystemonChip (SOC'2014), Oct. 2829, 2014, Tampere, Finland.

An EquivalencePreserving Transformation of Shift Registers,
in Proceedings of Sequences and Their Applications (SETA'2014), eds. K.U. Schmidt and A. Winterhof, LNCS 8865, 2014, pp. 187199, availible at Cryptology ePrint Archive, Report 2014/051, January 2014, http://eprint.iacr.org/2014/051.

EnergyEfficient Message Authentication for IEEE 802.15.4Based Wireless Sensor Networks, (with M. Näslund, G. Selander, V. Tsiatsis), in Proceedings of 32nd Nordic Microelectronics Conference NORCHIP (NORCHIP'2014), Oct. 2728, 2014, Tampere, Finland.

Evaluation of Alternative LBIST Flows: A Case Study, (with Nan Li, G. Carlsson), in Proceedings of 32nd Nordic Microelectronics Conference NORCHIP (NORCHIP'2014), Oct. 2728, 2014, Tampere, Finland.

An New Approach to Reliable FSRs Design, (with M. Liu), in Proceedings of 32nd Nordic Microelectronics Conference NORCHIP (NORCHIP'2014), Oct. 2728, 2014, Tampere, Finland.

AreaEfficient HighCoverage LBIST, (with N. Li), Microprocessors and Microsystems, vol. 38, issue 5, pp. 368374, Springer, July 2014.

Secure and Efficient LBIST for Feedback Shift RegisterBased Cryptographic Systems, (with M. Näslund, G. Selander), in Proceedings of
19th IEEE European Test Symposium (ETS'2014), May 2630, 2014, Paderborn, Germany.
 A Method for Generating Full Cycles by a Composition of NLFSRs, Design, Codes and Cryptography, Springer, 2014, DOI 10.1007/s1062301499473.

An Algorithm for Constructing a Smallest Register with NonLinear Update Generating a Given Sequence, (with N. Li), in Proceedings of IEEE International Symposium on MultipleValued Logic (ISMVL'2014), May 1921, 2014, Bremen.
2013

FaultTolerant Design, Springer, 2013, ISBN 9781461421122.
 Protecting Ring Oscillator Physical Unclonable Functions against Modelling Attacks, (with S. S. Mansouri), in Proceedings of Information Security and Cryptology
(ICISC2013), Seoul, Korea, November, 2729, 2013.

An Improved Hardware Implementation of the Grain128a Stream Cipher, (with S. S. Mansouri), in Information Security and Cryptology , Lecture Notes in Computer Science vol. 7839, eds. T. Kwon, M.K. Lee, and D. Kwon, Springer Berlin Heidelberg, 2013, pp. 278292.
 A Scalable Method for Constructing Galois NLFSRs with Period 2^{n}1 using CrossJoin Pairs,
IEEE Transactions on Information Theory, vol. 59, issue 1, 2013, pp. 703709.
 DoubleEdge Transformation for Optimized Power Analysis Suppression Countermeasures, (with S. S. Mansouri),
Digital Systems Design Conference (DSD'2013), Santander, Spain, September 46, 2013.
 A Faster ShiftRegister Alternative to Filter Generators, (with M. Liu),
Digital Systems Design Conference (DSD'2013), Santander, Spain, September 46, 2013.
 Embedding of Deterministic Test Data for InField Testing, (with N. Li),
ArXive Report 1302.6454, Jan 2013, http://arxiv.org/abs/1302.6454.
 An Algorithm for Constructing a Smallest Register with NonLinear Update Generating a Given Binary Sequence, (with N. Li),
ArXive Report 1306.5596, Jun 2013, http://arxiv.org/abs/1306.5596.
 An Improved Hardware Implementation of the Quark Hash Function, (with S. S. Mansouri),
RFIDSec'2013 , Lecture Notes in Computer Science vol. 8262, eds. M. Hutter, J.M. Schmidt, SpringerVerlag Berlin Heidelberg, 2013, pp. 113127.
 The Robustness of Balanced Boolean Networks,
(with M. Liu),
in Complex Networks: Studies in Computational Intelligence, Eds. Menezes, R., Evsukoff, A.,
Gonzalez, M. C., Springer, Berlin/Heidelberg, vol. 424, 2013, pp. 1930.
 A BDDBased Method for LFSR Parellelization with Application to Fast CRC Encoding,
(with S. S. Mansouri),
Journal of MultipleValued Logic and Soft Computing, vol 21, no. 56, 2013, pp. 561575.
 A Method for Generating Full Cycles by a Composition of NLFSRs,
Proceeding of International Workshop on Coding and Cryptography (WCC'2013), 1519 April 2013, Bergen, Norway.
 Secure Key Storage Using State Machines,
(with N. Li, S. S. Mansouri),
Proceedings of IEEE International Symposium on MultipleValued Logic (ISMVL'2013), May 2124, 2013, Toyama, Japan.
 OnChip AreaEfficient Binary Sequence Storage,
(with N. Li, S. S. Mansouri),
Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI'2013), May 24, 2013, Paris, France.

Design of a Terminal Solution for Integration of Inhome Healthcare Devices and Services towards the InternetofThings,
(with Pang, Z., P., Chen, Q., Zheng, L.),
Enterprise Information Systems, 2013, DOI: 10.1080/17517575.2013.776118.
2012
 A Method for Generating Full Cycles by a Composition of NLFSRs,
Cryptology ePrint Archive, Report 2012/492, August 2012, http://eprint.iacr.org/2012/492.
 Finding Attractors in Synchronous MultipleValued Networks Using SATbased Bounded Model Checking,
(with M. Liu, M. Teslenko),
Journal of MultipleValued Logic and Soft Computing, vol 19, no. 13, 2012, pp. 109133.
 Ring Oscillator Physical Unclonable Function with Multi Level Supply Voltages,
(with S. S. Mansouri), Proceedings of IEEE International Conference on Computer Design (ICCD'2012), Sept. 30  Oct. 3, 2012, Montreal, Quebec, Canada.
 An Architectural Countermeasure against Power Analysis Attacks for FSRBased Stream Ciphers, (with S. S. Mansouri), in Constructive SideChannel Analysis and Secure Design, Lecture Notes in Computer Science vol. 7275, eds. W. Schindler and S. Huss, Springer Berlin
Heidelberg, pp. 5468.
 An Improved Hardware Implementation of the Grain128a Stream Cipher,
(with S. S. Mansouri), in Information Security and Cryptology, Lecture Notes in Computer Science vol. 7839, eds. T. Kwon, M.K. Lee, and D. Kwon, Springer Berlin Heidelberg, 2012, pp. 278292.
 A List of MaximumPeriod NLFSRs,
Cryptology ePrint Archive, Report 2012/166, March 2012, http://eprint.iacr.org/2012/166.
 A BDDBased Approach to Constructing LFSRs for Parallel CRC Encoding,
(with S. S. Mansouri),
Proceedings of IEEE International Symposium on MultipleValued Logic (ISMVL'2012), Victoria, BC, Canada, May 1416, 2012, pp. 128  133.
 PowerSecurity Tradeoff in MultiLevel Power Analysis Countermeasures for FSRBased Stream Ciphers,
(with S. S. Mansouri),
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2012),
May 2023, 2012, Seoul, Korea.
2011
 A Scalable Method for Constructing Galois NLFSRs with Period 2^{n}1 using CrossJoin Pairs,
Cryptology ePrint Archive, Report 2011/632, November 2011, http://eprint.iacr.org/2011/632.
 Synthesis of Parallel Binary Machines,
Proceedings of International Conference on ComputerAided Design (ICCAD'2011),
November 710, 2011, San Jose, CA, USA, pp. 200206.
 AIG Rewriting Using 5Input Cuts, (with N. Li)
Proceedings of International Conference on Computer Design (ICCD'2011),
October 9  12, 2011, Amherst, MA, USA, pp. 429430
 Synthesis of Binary Machines,
IEEE Transactions on Information Theory, vol. 57, no. 10, 2011, pp. 68906893.
 A SATBased Algorithm for Finding Attractors in Synchronous Boolean Networks,
(with M. Teslenko),
IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol. 8, no. 5, 2011, pp. 13931399.
 RuleBased Optimization of ANDXOR Expressions,
(with D. Knysh),
Journal Facta Universitatis, vol. 24, no. 3, December 2011, pp. 437449.
 A Countermeasure Against Power Analysis Attacks for FSRBased Stream Ciphers,
(with S. S. Mansouri),
Notes of Symmetric Key Encryption Workshop (SKEW'2011), 16  17 February 2011
Lyngby, Denmark.
 Integrated Logic Synthesis Using Simulated Annealing,
(with P. Färm, A. Kuehlmann),
Proceedings of Great Lakes Symposium on VLSI (GLSVLSI'2011),
May 24 2011, Lausanne, Switzerland, pp. 407410.
 A Countermeasure Against Power Analysis Attacks for FSRBased Stream Ciphers,
(withe S. Mansouri),
Proceedings of Great Lakes Symposium on VLSI (GLSVLSI'2011),
May 24 2011, Lausanne, Switzerland, pp. 235240.
 RuleBased Optimization of ANDXOR Expressions,
(with D. Knysh),
Notes of 2011 ReedMuller Workshop (RM'2011),
May 2526, 2011, Tuusula, Finland, pp. 4549.
 AIG Rewriting Using 5Input Cuts, (with N. Li)
Notes of 20th International Workshop on Logic and Synthesis (IWLS'2011),
June 3  5, 2011, San Diego, CA, USA.
 Synthesis of Parallel Binary Machines,
Notes of 20th International Workshop on Logic and Synthesis (IWLS'2011),
June 3  5, 2011, San Diego, CA, USA.
 Synthesis of Parallel Binary Machines,
ArXive ePrint Technical Report 1009.5802, May 2011, http://arxiv. org/abs/1105.4514.
2010
 Synthesis of Binary KStage Machnies,
ArXive ePrint Technical Report 1009.5802, Sept. 2010, http://arxiv. org/abs/1009.5802.
 Finding Matching Initial States for Equivalent NLFSRs in the Fibonacci and the Galois Configurations,
IEEE Transactions on Information Theory, vol. 56, no. 6, 2010, pp. 29612967.
 An Algorithm for Constructing a Fastest Galois NLFSR Generating a Given Sequence,
(with J.M.,Chabloz, S. Mansouri),
Sequences and Their Applications (SETA'2010), Eds. C. Carlet and A. Pott., LNCS 6338, 2010, pp. 4155.
 Pulse Latch Based FSRs for LowOverhead Hardware Implementation of Cryptographic Algorithms,
(with S. S. Mansouri),
IEEE International Conference of Computer Design (ICCD'2010), Amsterdam, the Netherlands
Oct. 36, 2010.
 Pulse Latch Based Implementation of Trivium for RFID Authentication,
(with S. S. Mansouri),
Notes of 6th Workshop on RFID Security (RFIDSec'2010), Istanbul, Turkey,
June 7  9, 2010.
 Finding Attractors in Synchronous MultipleValued Networks Using SATbased Bounded Model Checking,
(with M. Teslenko, M. Liu),
Proceedings of IEEE International Symposium on MultipleValued Logic (ISMVL'2010), Barcelona, Spain, May 2628, 2010, pp. 144  149 (best paper award).
 Pulse Latch Based FSRs for LowOverhead Hardware Implementation of Cryptographic Algorithms,
(with S. S. Mansouri),
Notes of International Workshop in Logic and Synthesis (IWLS'2010),
Irvine, CA, USA, June 1820, 2010.
 An NLFSR ReSynthesis Algorithm for Delay Optimization,
(with J.M.,Chabloz, S. Mansouri),
Notes of International Workshop in Logic and Synthesis (IWLS'2010),
Irvine, CA, USA, June 1820, 2010.
 An Improved Hardware Implementation of the Grain Stream Cipher,
(with S. S. Mansouri),
Proceedings of Euromicro Conference on Digital System Design (DSD'2010), Lille, France,
Sept. 13, 2010.
2009

A Transformation from the Fibonacci to the Galois NLFSRs,
IEEE Transactions on Information Theory, vol. 55, no. 11, 2009, pp. 52635271.
 How to SpeedUp Your NLFSRBased Stream Cipher,
Proceedings of Design and Test in Europe (DATE'2009),
April 2024, 2009, Nice, France, pp. 878881.
 Finding Matching Initial States for Equivalent NLFSRs in the Fibonacci and the Galois Configurations,
ArXive ePrint Technical Report 0903.3182, March 2009, arXiv:0903.3182.
 A SATBased Algorithm for Computing Attractors in Synchronous Boolean Networks,
(with M. Teslenko), ArXive ePrint Technical Report 0901.4448, January 2009, arXiv:0901.4448.
2008
 A Computational Scheme Based on Random Boolean Networks,
(with M. Teslenko, H. Tenhunen),
Transactions on Computational Systems Biology X, Eds. C. Priami et al., LNBI 5410, 2008, pp. 4158.
 SelfOrganization for FaultTolerance,
Proceedings of Third International Workshop on SelfOrganizing Systems (IWSOS'2008),
December 1012, 2008, Vienna, Austria, Eds. K. A. Hummel and J. Sterbenz, LNCS 5343, 2008, pp. 145157.
 BioInspired FaultTolerance,
Proceedings of IEEE/ACM International Conference on BioInspired Models of Network, Information, and Computing Systems (BIONETICS'2008),
November 2528, 2008, Hyogo, Japan.
 Analysis and Synthesis of (n,k)NonLinear Feedback Shift Registers,
(with M. Teslenko, H. Tenhunen),
Proceedings of Design, Automation and Test in Europe (DATE'2008),
1014 March 2008, Munich, Germany, pp. 12861291.
 How to Increase the Throughput of an NLFSRbased Stream Cipher,
Extended Abstracts of the Second Workshop on Mathematical Cryptology (WMC'2008),
Eds. A. Ibeeas and J. Gutierrez, October 2325, 2008, Santander, Spain, pp. 8689.
 Learning Robustness from Gene Regulatory Networks,
Abstract Book of the 9th International Conference on Systems Biology (ICSB'2008),
August 2228, 2008, Gothenburg, Sweden, p. 179.
 Learning FaultTolerance from Nature,
Proceedings of International Biennial Baltic Electronics Conference (invited talk),
2008, October 68, 2008, Tallinn, Estonia, pp. 5158.
 NLFSR ReSynthesis for High Throughput,
Notes of International Workshop on Logic and Synthesis (IWLS'2007),
June 46, 2008, Lake Tahoe, CA, USA.
 Synthesis of NLFSRBased PseudoRandom Bit Generators for Stream Ciphers,
Proceedings of International Symposium on Applied Computing (IADIS'2005),
1013 April 2008, Algarve, Portugal.
 An Equivalence Preserving Transformation from the Fibonacci to the Galois NLFSRs,
ArXive ePrint Technical Report 0801.4079, January 2008, arXiv:0801.4079.
2007
 A Computational Model Based on Random Boolean Networks,
(with M. Teslenko, H. Tenhunen),
Proceedings of International Conference on BioInspired Models of Network, Information, and
Computing Systems (BIONETICS'2007),
December 1013, 2007, Budapest, Hungary.
 FIREwork: Redundancy Identification and Removal for Large
Combinational Circuits,
(with M. Teslenko, H. Tenhunen),
Notes of International Workshop on Logic and Synthesis (IWLS'2007),
May 30  June 1, 2007, San Diego, CA, USA, pp. 388396.
 Evaluation and Comparison of Threshold Logic Gates,
(with V. Lirigis),
Proceedings of 37th IEEE International Symposium on MultipleValued Logic
(ISMVL'2007), May 1416, 2007, Oslo, Norway, pp. 5256.
 A Dynamic Network Model for Nanoscale Systems,
(with H. Tenhunen),
European NanoSystems'2007,
December 34, 2007, Paris, France.
2006

Integrated Logic Synthesis Using Simulated Annealing,
(with P. Färm and A. Kuehlmann),
Notes of International Workshop on Logic Synthesis,
June 79, 2006, Vail, Colorado, USA.
 Random MultipleValued Networks: Theory and Applications,
Proceedings of 36th IEEE International Symposium on MultipleValued Logic
(ISMVL'2006), May 1720, 2006, Singapore, pp. 2733.
 An Efficient Algorithm for Computing Common DoubleVertex Dominators,
(with M. Teslenko, H. Tenhunen),
Proceedings of International Symposium on Applied Computing (IADIS'2006),
February 2528, 2006, San Sebastian, Spain, pp. 3442.
 A Computational Scheme Based on Random Boolean Networks on the Critical Line,
(with H. Tenhunen),
Proceedings of International Symposium on Applied Computing (IADIS'2006),
February 2528, 2006, San Sebastian, Spain, pp. 273281.
 A PolynomialTime Algorithm for Computing Bound
Sets,
(with R. Krenz),
IEE Proceedings  Circuits, Devices and Systems}, vol. 153, issue 2, April
2006, pp. 179184.
2005
 Kauffman Networks: Analysis and Applications,
(with M. Teslenko, A. Martinelli),
Proceedings of International Conference on ComputerAided Design (ICCAD'2005),
November 610, 2005, San Jose, CA, USA, pp. 479484.
 Compositional Properties of Random Boolean Networks,
(with M. Teslenko)
Physical Review E, vol. 71, issue 2, May 2005, 056116.
 Boundset preserving ROBDD variable orderings may not be optimum,
(with M. Teslenko, A. Martinelli),
IEEE Transactions on Computers, February 2005, vol. 54, no. 2, pp. 236238.

From Living Cells to FaultTolerant Systems: Computing Based on Gene
Regulatory Networks,
Proceedings of Swedish SystemonChip Conference (SSoCC'05),
April 1819, 2005, Tammsvik, Sweden.

Computing Common DoubleVertex Dominators in Circuit Graphs,
(with M. Teslenko),
Notes of International Workshop on Logic Synthesis,
June 810, 2005, Lake Arrowhead, CA, USA.

Kauffman Networks: From Nature to Electronics,
(with M. Teslenko),
Notes of International Workshop on Logic Synthesis,
June 810, 2005, Lake Arrowhead, CA, USA.
 Modeling Gene Regulatory Systems by Random Boolean Networks,
Proceedings of SPIE Bioengineered and Bioinspired Systems II,
vol. 5839, June 2005, pp. 5665.
 Phylogenetic Networks with EdgeDisjoint Recombination Cycles,
Proceedings of SPIE Bioengineered and Bioinspired Systems II,
vol. 5839, June 2005, pp. 381388.
 Logic Optimization Technique for Molecular Cascades,
(with P. Färm, H. Tenhunen),
Proceedings of SPIE Nanotechnology II,
vol. 5838, June 2005, pp. 95104.
 An Efficient Structural Technique for Boolean Decomposition,
(with A. Martinelli),
Proceedings of SPIE VLSI Circuits and Systems II,
vol. 5837, June 2005, pp. 913918.
 Computing a Perfect Input Assignment for Probabilistic Verification,
(with M. Teslenko, H. Tenhunen),
Proceedings of SPIE VLSI Circuits and Systems II,
vol. 5837, June 2005, pp. 929936.
 An Efficient Algorithm for Finding DoubleVertex Dominators in Circuit Graphs,
(with M. Teslenko),
Proceedings of Design and Test in Europe (DATE'2005),
March 711, 2005, Munich, Germany, pp. 406411.
 Structural Testing Based on Minimum Kernels,
Proceedings of Design and Test in Europe (DATE'2005),
March 711, 2005, Munich, Germany, pp. 11681171.
 Bound Set Selection and Circuit ReSynthesis for Area/delay Driven Decomposition,
(with A. Martinelli),
Proceedings of Design and Test in Europe (DATE'2005)
March 711, 2005, Munich, Germany, pp. 430431.
 LinearTime Algorithm for Computing Minimum Checkpoint Sets for SimulationBased Verification of HDL Programs,
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2004),
May 2326, 2005, Kobe, Japan.
 Computing Attractors in Complex Dynamic Networks,
(with M. Teslenko, H. Tenhunen),
Proceedings of International Symposium on Applied Computing (IADIS'2005),
February 2325, 2005, Algarve, Portugal, pp. 535543.
 Improved Boolean Function Hashing based on MultipleVertex Dominators,
(with R. Krenz),
Proceedings of Asia and South Pacific Design Automation Conference (ASPDAC'2005), January 2123, 2005. Shanghai, China.
 A Fast Algorithm for Finding Common MultipleVertex Dominators in Circuit Graphs,
(with R. Krenz),
Proceedings of Asia and South Pacific Design Automation Conference (ASPDAC'2005), January 2123, 2005. Shanghai, China.
 Logic Optimization Using RuleBased Randomized Search,
(with P. Färm, A. Kuehlmann),
Proceedings of Asia and South Pacific Design Automation Conference (ASPDAC'2005), January 2123, 2005. Shanghai, China.
2004
 Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth,
(with M. Teslenko),
Proceedings of International Conference on ComputerAided Design (ICCAD'2004),
November 711, 2004, San Jose, CA, USA.
 LUT FPGA technology mapping for area minimization with optimum depth,
(with M. Teslenko),
Notes of International Workshop on Logic Synthesis (IWLS'2004),
June 24, 2004, San Diego, CA, USA, pp. 2228.
 Efficient computation and representation of doublevertex dominators in circuit graphs,
(with M. Teslenko),
Notes of International Workshop on Logic Synthesis (IWLS'2004),
June 24, 2004, San Diego, CA, USA, pp. 4450.
 On relation between nondisjoint decomposition and
multiplevertex dominators,
(with M. Teslenko, A. Martinelli),
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2004),
May 2326, 2004, Vancouver, Canada.
 A polynomialtime algorithm for nondisjoint decomposition of
multiplevalued functions,
Proceedings of 34th IEEE International Symposium on MultipleValued Logic (ISMVL'2004),
May 1921, 2004, Toronto, Canada, pp. 309315.
 Disjointsupport Boolean decomposition combining functional and structural methods,
(with A. Martinelli, R. Krenz),
Proceedings of Asia and South Pacific Design Automation Conference (ASPDAC'2004), January 2730, 2004. Yokohama, Japan.
 Trading completeness for capacity using probabilistic techniques,
(with R. Krenz),
Proceedings of Designing Correct Circuits Workshop (DCC'2004), 2728 March 2004, Barcelona, Spain.
 TOP: An algorithm for threelevel combinational logic optimization,
(with Ellervee, P., Miller, D.M., Muzio, J.C., Sullivan, A. J.),
IEE Proceedings  Circuits, Devices and Systems, vol. 5, no. 4, pp. 307314,
August 2004.
 Probabilistic equivalence checking of multiplevalued functions,
(with Sack, H.),
Journal of MultipleValued Logic and Soft Computing,
vol. 10, no. 4, pp. 395414, 2004.
2003
 Boolean decomposition based on cyclic chains,
(with Teslenko, M., Karlsson, J.),
Proceeding of International Conference on Computer Design (ICCD'2003),
October 1113, 2003, San Jose, CA, pp. 504510.
 Probabilistic verification based on function hashing,
(with Krenz, R.),
Proceedings of of NORCHIP'03,
November 2003, Riga, Latvia.
 Two fault tolerant MIPS processor architectures for NOC applications,
(with Mathew, J., Tomas, J. ),
Proceedings of of NORCHIP'03,
November 2003, Riga, Latvia.
 RothKarp decomposition combining functional and structural techniques,
(with A. Martinelli, R. Krenz),
Notes of International Workshop on Logic Synthesis,
May 2003, pp. 1823.
 Fast multilevel logic optimization using local transformations,
(with P. Färm),
Notes of International Workshop on Logic Synthesis,
May 2003, pp. 120126.
 Implementation of multiplevalued functions using literalsplitting technique,
Proceedings of 33rd IEEE International Symposium on MultipleValued Logic,
May 2003, pp. 711.
 Fast algorithm for computing spectral transforms of Boolean and multiplevalued functions,
(with R. Krenz, A. Kuehlmann),
Proceedings of 33rd IEEE International Symposium on MultipleValued Logic,
May 2003, 334343.
 Totally selfchecking 1outofn checker with application to the design of fault tolerant FIR filter,
(with J. Mathew),
Proceedings of the International Workshop on the Applications of the ReedMuller Expansion in Circuit Design,
March 2003.
 Logic Optimization and Technology Mapping for CAEN,
(with Färm, P., Tenhunen, H.),
Proceedings of NanoTech´2003,
February 2003.
 Electronic nanotechnology based on nonbinary principles,
(with J. Mathew, Tenhunen, H.),
Proceedings of NanoTech´2003,
February 2003.
 A BDDbased fast heuristic algorithm for disjoint decomposition,
(with T. Bengtsson, A. Martinelli),
Proceedings of Asia and South Pacific Design Automation Conference, ASPDAC03,
January 2003.
2002
 Circuitbased Evaluation of the Arithmetic Transform of Boolean Functions,
(with Krenz, R., Kuehlmann, A.),
Notes of International Workshop on Logic Synthesis,
June 47, 2002, New Orleans, Louisiana, pp. 321327.
 A Fast Heuristic Algorithm for Disjoint Decomposition of Boolean Functions,
(with Bengtsson, T., Martinelli, A.),
Notes of International Workshop on Logic Synthesis,
June 47, 2002, New Orleans, Louisiana, pp. 5157.
 Technology Mapping for Chemically Assembled Electronic Nanotechnology,
(with Färm, P.),
Notes of International Workshop on Logic Synthesis,
June 47, 2002, New Orleans, Louisiana, pp. 121125.
 NonSilicon NonBinary Computing: Why not?,
(with Jamal. Y., Mathew. J.),
Proceedings of 1st Workshop on NonSilicon Computation,
February 3, 2002, Boston, USA, pp. 2329.
 Composition Trees in Finding Best Variable Orderings for ROBDDs,
Proceedings of DATE'2002,
March 48, 2002, Paris, France.
 A Conjunctive Canonical Expansion of MultipleValued Functions,
(with Färm, P.),
Proceedings of 32nd International Symposium on MultipleValued Logic,
May 1418, 2002, Boston, USA.
 MultipleValued Logic Synthesis and Optimization,
Logic Synthesis and Verification, Eds.: S. Hassoun and T. Sasao,
Kluwer Academic Publishers, 2002, pp. 89114.
 Onthefly proper cut recognition based on circuit graph analysis,
(with Krenz, R.),
Proceedings of of NORCHIP'02,
November 2002, Copenhagen, Denmark.
 RothKarp decomposition of large Boolean functions with application to logic design,
(with A. Martinelli, T. Bengtsson, A. J. Sullivan),
Proceedings of of NORCHIP'02,
November 2002, Copenhagen, Denmark.
 Totally selfchecking 1outofn checker with application to fault tolerant design,
(with J. Mathew),
Proceedings of of NORCHIP'02,
November 2002, Copenhagen, Denmark.
 Selfchecking checker for 1outofn code based on currentmode CMOS logic,
(with J. Mathew),
Proceedings of Defect and Fault Tolerance in VLSI Systems Conference, DFT2002,
Vancouver, Canada, November 2002.
 Conjunctive decomposition for multiplevalued input binaryvalued output functions,
(with P. Färm, R. S. Stankovic, and J. T. Astola),
Proceedings of International TICSP Workshop on Spectral Methods and Multirate Signal Processing,
Toulouse, France, September 2002, pp. 227234.
2001
 Formal Verification Using Probabilistic Techniques,
(with Krenz, R.),
Proceedings of of NORCHIP'01,
November 1213, 2001, Stockholm, Sweden, pp. 258264.
 A Sufficient Condition for Detection of XORType Logic,
(with Bengtsson, T.),
Proceedings of of NORCHIP'01,
November 1213, 2001, Stockholm, Sweden, pp. 271279.
 Programmable Logic in FaultTolerant Design,
(with Bengtsson, T., Krenz, R.),
Proceedings of 4th Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD'2001),
September 1113, 2001, Laurel, Maryland, USA.
 An Algorithm for Detecting XORType Logic,
(with Bengtsson, T.),
Proceedings of 5th International Workshop on the Applications of the ReedMuller Expansion in Circuit Design,
August 1011, 2001, Starkville, Mississippi, USA, pp. 271276.
 Minimization of MultipleValued Functions in Post Algebra,
(with Jiang, Y., Brayton, R.),
Proceedings of International Workshop on Logic Synthesis,
June 1215, 2001, Lake Tahoe, California, pp. 132138.
 A Design Technique for HighPerformance SelfChecking Combinational Circuits,
Proceedings of IEEE European Test Workshop,
May 29  June 1, 2001, Stockholm, Sweden, pp. 1113.
 Power Efficient InterMode Communication for DigitSerial DSP Architectures in DeepSubmicron Technology,
(with Ben Dhaou, I., Tenhunen, H.),
Proceedings of 31st IEEE International Symposium on MultipleValued Logic,
May 2527, 2001, Warsaw, Poland, pp. 6166.
2000
 Easily Testable MultipleValued Logic Circuits,
(with Muzio, J. C.),
IEEE Transactions on Computers,
49, 2000, pp. 12851289.
 A Comment on "GraphBased Algorithm for Boolean Function Manipulation",
(with Macchiarulo, L.),
IEEE Transactions on Computers,
49, 2000, pp. 12901292.
 Upper Bound on the Number of Products in a SumofProduct Expansion of MultipleValued Functions,
MultipleValued Logic, An International Journal,
5, 2000, pp. 349364.
 A Sufficient Condition for Detecting ANDORANDType Logic,
(with Millberg, M., Sullivan, A.J.),
Proceedings of International Workshop of Logic Synthesis,
May 31  June 2, 2000, Dana Point, CA, pp. 147151.
 Representation of MultipleValued Functions with ModpDecision Diagrams,
(with Sack, H., Meinel, C.),
Proceedings of International Workshop of Logic Synthesis,
May 31  June 2, 2000, Dana Point, CA, pp. 341348.
 Probabilistic Verification of MultipleValued Functions,
(with Sack, H.),
Proceedings of 30th IEEE International Symposium on MultipleValued Logic,
May 2325, 2000, Portland, Oregon, pp. 460467.
 Modp Decision Diagrams: A Data Structure for MultipleValued Functions,
(with Sack, H., Meinel, C.),
Proceedings of 30th IEEE International Symposium on MultipleValued Logic,
May 2325, 2000, Portland, Oregon, pp. 233239.
 TOP: An Algorithm for ThreeLevel Optimization of PLDs,
(with Ellervee, P., Miller, D.M., Muzio, J. C.),
Proceedings of Design, Automation and Test in Europe Conference and Exhibition,
March 2830, 2000, Paris, France, p. 751 (best poster award).
1999
 MultipleValued Logic in VLSI: Challenges and Opportunities,
Proceedings of NORCHIP'99 (invited talk),
November 89, 1999, Oslo, Norway, pp. 340350.
 A New Decomposition of Boolean Functions,
Proceedings of NORCHIP'99,
November 89, 1999, Oslo, Norway, pp. 310316.
 Composition of Reduced Ordered Binary Decision Diagrams,
Proceedings of International Workshop on Logic Synthesis,
June 2730, 1999, Lake Tahoe, California, pp. 173176.
 A Fast Algorithm for ThreeLevel Logic
Optimization
(with Ellervee, P.),
Proceedings of International Workshop on Logic Synthesis,
June 2730, 1999, Lake Tahoe, California, pp. 151154.
 On Disjoint Covers and ROBDD Size
(with Miller, D.M.),
Proceedings of 1999 IEEE Pacific Rim Conference on Communications, Computer and Signal Processing,
August 2325, 1999, Victoria, B.C., Canada, pp. 162164.
 AOXMINMV: A Heuristic Algorithm for ANDORXOR Minimization
(with Miller, D.M., Muzio, J. C.),
Proceedings of 4th International Workshop on the Applications of the ReedMuller Expansion in Circuit Design,
August 2021, 1999, Victoria, B.C., Canada, pp. 3754.
 Evaluation of mvalued Fixed Polarity Generalizations of ReedMuller Canonical Form,
Proceedings of 29th International Symposium on MultipleValued Logic,
May 2022, 1999, Freiburg, Germany, pp. 9298.
1998
 The Spectrality Decision Problem
(with Muzio, J.C.),
International Journal Approximation Theory and Applications,
14:3, 1998, pp. 7384.
 On Dependable Strategy for Dynamic Reordering Algorithms
(with Miller, D.M.),
Proceedings of 7th International Workshop on on PostBinary ULSI Systems,
Fukuoka, Japan, May 26, 1998, pp. 4648.
1997
 AOXMIN: A ThreeLevel Heuristic ANDORXOR Minimizer for Boolean Functions
(with Miller, D.M., Muzio, J.C.),
Proceedings of 3rd International Workshop on the Applications of the ReedMuller Expansion in Circuit Design,
Oxford, UK, Sept. 1920, 1997, pp. 209218.
 On the Relation Between Disjunctive Decomposition and ROBDD Variable Ordering
(with Miller, D.M., Muzio, J.C.),
Proceedings of 1997 IEEE Pacific Rim Conference on Communications, Computer and Signal Processing,
Victoria, B.C., Canada, August 2022, 1997, pp. 688691.
 On the Best ROBDD Variable Ordering for Functions with Disjunctive Decompositions
(with Miller, D.M., Muzio, J.C.),
IEE Journal of Electronics Letters,
33, 1997, pp. 11981200.
 Finding Composition Trees for MultipleValued Functions
(with Muzio, J.C. and von Stengel, B.),
Proceedings of 27th International Symposium on MultipleValued Logic,
1997, pp. 1926.
1996
 Testability of Generalized MultipleValued ReedMuller Circuits
(with Muzio, J.C.),
Proceedings of 26th International Symposium on MultipleValued Logic,
1996, pp. 5661.
 Generalized ReedMuller Canonical Form for a MultipleValued Algebra
(with Muzio, J.C.),
MultipleValued Logic, An International Journal,
1, 1996, pp. 6584.
1995 and before
 Upper bound on number of products in ANDORXOR expansion of logic functions
(with Miller, D.M., Muzio, J.C.),
IEE Journal of Electronics Letters,
31, 1995, pp. 541542.
 The Evaluation of Full Sensitivity for Test Generation in MVL Circuits
(with Gurov, D.B., Muzio, J.C.),
Proceedings of 25th International Symposium on MultipleValued Logic,
1995, pp. 104109.
 Full Sensitivity and Test Generation for MultipleValued Logic Circuits
(with Gurov, D.B., Muzio, J.C.),
Proceedings of 24th International Symposium on MultipleValued Logic,
1994, pp. 284289.
 A Device for Computing of Implicants
(with Bondar I.N., Shmerko, V.P., Janushkevich, S.N.),
An author's certificate of USSR,
No 1686460, G 06 F 15/353, 1991 (in Russian).