Publications

Micro-architecture, CGRAs, NNs, NOCs

• Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, M Martina, “NACU: A Non-Linear Arithmetic Unit for Neural Networks, 57th DAC 2020
• S M. A. H. Jafri, H Hassan, Ahmed Hemani, O Mutlu (2020), “Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators NOCS”, ACM Transactions on Architecture and Code Optimization (TACO), 18 (1), 1-29
• Farahini, N.; Shuo Li; Tajammul, M.A.; Shami, M.A.; Guo Chen; Hemani, A.; Wei Ye, “39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation,” Circuits and Systems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.1448,1451, 19-23 May 2013
• S M. A. H. Jafri, Ahmed Hemani, K Paul, and N Abbas, “MOCHA: Morphable locality and compression aware architecture for convolutional neural networks” (2017). IEEE IPDPS 2017
• Nasim Farahini, Ahmed Hemani, Hassan Sohofi, Seyed M. A. H. Jafri, Muhamamd Adeel Tajammul, Kolin Paul, “Parallel Distributed Scalable Address Generation Scheme for a Coarse Grain Reconfigurable Computation and Storage Fabric,” Microprocessors and Microsystems Journal, Elsevier, Nov. 2014.
• Jafri, Syed MAH; Guang, Liang; Hemani, Ahmed; Paul, Kolin; Plosila, Juha; Tenhunen, Hannu; “Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes”, Microprocessors and Microsystems, 37,8, 811-822, 2013, Elsevier
• Tajammul, Muhammad Adeel; Jafri, Syed MAH; Hemani, Ahmed; Plosila, Juha; Tenhunen, Hannu; “Private configuration environments (PCE) for efficient reconfiguration, in CGRAs”, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors”, 227-236, 2013, IEEE
• Tajammul Muhammad Adeel, Shami Muhammad Ali, Hemani Ahmed. Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture, Embedded Multicore Socs (MCSoC), 2012 IEEE 6th International Symposium on, 67-74
• Shami, Muhammad Ali; Hemani, Ahmed; “Classification of massively parallel computer architectures”, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 344-351, 2012, IEEE
• Muhammed Ali Shami, Ahmed Hemani. Control Scheme in a Coarse Grain Reconfigurable Architecture. 22nd Intl Symposium on Computer Architecture and High Performance Computing, Brasil Oct. 27-30 2010.
• Muhammed Ali Shami, Ahmed Hemani. Partially Reconfigurable Interconnection Network for Dynamically Reprogrammable Resource Array in IEEE 8th International Conference on ASIC, October 20-23, 2009.

Clocking and Power Management

• Jafri, S.M.A.H.; Tajammul, M.A.; Hemani, A.; Paul, K.; Plosila, J.; Tenhunen, H., “Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs,” Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on , vol., no., pp.104,112, 15-18 July 2013
• Chabloz, Jean-Michel; Hemani, Ahmed; “Low-latency No-handshake GALS interfaces for fast-receiver links”, 2012, 25th International Conference on VLSI Design, 191-196, 2012, IEEE
• Jafri, Syed MAH; Guang, Liang; Jantsch, Axel; Paul, Kolin; Hemani, Ahmed; Tenhunen, Hannu; “Self-adaptive Noc Power Management with Dual-level Agents-Architecture and Implementation.”, PECCS, 450-458 2012
• Anagnostopoulos, Iraklis; Chabloz, Jean-Michel; Koutras, Ioannis; Bartzas, Alexandros; Hemani, Ahmed; Soudris, Dimitrios; “Power-aware dynamic memory management on many-core platforms utilizing DVFS ACM Transactions on Embedded Computing Systems (TECS) 13 1s 25-Jan 2013 “ACM New York, NY, USA.
• Chabloz, Jean-Michel; Hemani, Ahmed; “Power management architecture in McNoC Scalable Multi-Core Architectures” 55-80, 2012, “Springer, New York, NY”

Synchoros VLSI Design - SiLago Framework

• Hemani, Ahmed, Syed Mohammed Asad Hassan Jafri, and Shayesteh Masoumian. “Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable.” In Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, p. 8. ACM, 2017.
• J A González, D Stathis, A Hemani, “Synthesis of predictable global NoC by abutment in synchoros VLSI design”, 2021 15th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 61-66
• Stathis, Dimitrios; Chaourani, Panagiotis; Jafri, Syed MAH; Hemani, Ahmed; ,Clock Tree Generation by Abutment in Synchoros VLSI Design,2021 IEEE Nordic Circuits and Systems Conference (NorCAS),1-7,2021,IEEE
• Hemani, Ahmed; Farahini, Nasim; Jafri, Syed MAH; Sohofi, Hassan; Li, Shuo; Paul, Kolin; ,The siLago solution: Architecture and design methods for a heterogeneous dark silicon aware coarse grain reconfigurable fabric,The Dark Side of Silicon,,,47-94,2017,”Springer, Cham”
• Nasim Farahini, Ahmed Hemani, Hassan Sohofi, Li Shuo., Physical Design Aware System Level Synthesis of Hardware. SAMOX XV, June 2015, Samos Greece.

Computation in Memristor

• Deyu Wang, Jiawei Xu, Dimitrios Stathis, Lianhao Zhang, Feng Li, Anders Lansner, Ahmed Hemani, Yu Yang, Pawel Herman and Zhuo Zou, “Mapping the BCPNN Learning Rule to a Memristor Model”, Frontiers Neurosciece, 09 December 2021, https://doi.org/10.3389/fnins.2021.750458
• J Xu, D Wang, F Li, L Zhang, D Stathis, Y Yang, Y Jin, A Lansner, A Hemani, A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation, IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021

Design methods for massively parallel architectures

• Omer Malik, Ahmed Hemani. “A Library Development Framework for a Coarse Grain Reconfigurable Architecture”. VLSI Design, Chennai. India. 2011.
• Omer Malik; Ahmed Hemani, “A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture,” Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on , vol., no., pp.1,6, Aug. 30 2012-Sept. 2 2012
• Shuo Li; Hemani, A., “Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework,” Digital System Design (DSD), 2013 Euromicro Conference on , vol., no., pp.11,17, 4-6 Sept. 2013
• Shuo Li; Farahini, N.; Hemani, A.; Rosvall, K.; Sander, I., “System level synthesis of hardware for DSP applications using pre-characterized function implementations,” Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013 International Conference on , vol., no., pp.1,10, Sept. 29 2013-Oct. 4 2013
• Farahini, Nasim, Ahmed Hemani, Hassan Sohofi, Syed MAH Jafri, Muhammad Adeel Tajammul, and Kolin Paul. “Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric.” Microprocessors and Microsystems 38, no. 8 (2014): 788-802.
• Malik, Omer; Hemani, Ahmed; “A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 06-Jan 2012, IEEE

Custom Supercomputer for Artificial neural networks

• A Hemani, M Shafique, K Paul (2020), “Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks”, Journal of Signal Processing Systems, 1-3
• S M. A. H. Jafri, H Hassan, Ahmed Hemani, O Mutlu (2020), “Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators NOCS”, ACM Transactions on Architecture and Code Optimization (TACO), 18 (1), 1-29.
• Y Yang, D Stathis, R Jordão, A Hemani, A Lansner (2020), “Optimizing BCPNN Learning Rule for Memory Access”, Frontiers in Neuroscience 14, 878
• Lansner, A.; Hemani, A.; Farahini, N., “Spiking brain models: Computation, memory and communication constraints for custom hardware implementation,” Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific , vol., no., pp.556,562, 20-23 Jan. 2014
• Farahini, N.; Hemani, A.; Lansner, A.; Clermidy, F.; Svensson, C., “A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain,” Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific , vol., no., pp.578,585, 20-23 Jan. 2014
• Jafri, Syed Mohammad Asad Hassan, Ahmed Hemani, Kolin Paul, and Naeem Abbas. “MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks.” In Parallel and Distributed Processing Symposium (IPDPS), 2017 IEEE International, pp. 276-286. IEEE, 2017.