Ahmed Hemani received his PhD from KTH (Royal Institute of Technology, Stockholm, Sweden) in 1993 and is currently a Professor in Electronic Systems Design at the School of EECS, KTH.

He has worked extensively in the industry (Digital Innovations/National Semiconductors, ABB, Ericsson, NewLogic, and Philips Semiconductors). In these companies, he worked on a cross-development environment, designed Embedded Systems for Process Contro,l baseband ASIC design for GSM, Bluetooth and 802.11a standards. In his last assignment at Philips Semiconductors (now NXP), he was the chip architect of the test-chip version of the Philips flagship Wireless Multi-media application processor, Energizer/Nexperia, in 65 nm technology. Nexperia was one of the first chips to use power-gating and dynamic voltage frequency scaling. He was part of three start-ups: Synthesia, Spirea and ELSIP.

As part of his academic research, he has contributed to design automation, novel architectural concepts, clocking and power management. His PhD thesis was on High-Level Synthesis, which used Kohonen’s self-organizing maps for scheduling and binding. This HLS tool was the basis for a start-up called Synthesia AB, which was acquired by CADENCE, whose first HLS product, Visual Architect, was based on this HLS tool. He has also contributed to automated synthesis from SDL and Grammar-based design methods.

While working at Ericsson, he observed the transition from Algorithm on a chip, where both computation and interconnect were hardwired, to systems-on-a-chip, where computation became programmable, but the interconnect remained hardwired. Based on this observation, he proposed that the next logical step would be to make both computation and interconnect programmable and called such architectures as Networks on Chip. He wrote the first paper on Networks On Chip with his colleagues from KTH and Ericsson.

He has also contributed to Globally Asynchronous Locally Synchronous Design Style. Later, he contributed to a more practical version of (GALS), called Globally Ratiochronous and Locally Synchronous (GRLS). GRLS, like GALS, enables latency insensitive synchronization among synchronous islands but comes with no round-trip delay penalty that plagues GALS. GRLS also does not require any special cells, like the Mueller C element, to implement asynchronous communication. TI and Ericsson adopted GRLS in a test chip for Ericsson’s base stations. GRLS was also the basis for a novel power management architecture that allowed dynamic voltage and clock domain boundaries.

Recently, he has focused on a novel synchoros VLSI design style that is the basis for a Lego-inspired design framework called SiLago (Silicon Lego), see SiLago for more details.

He is a senior member of IEEE and was Philips Semiconductors representative in the Schema Working Group of the SPIRIT consortium in 2004-2005.