Ongoing Projects

Here you can find a list of the projects I am currently working on as well as the ones that already finished.


APROPOS is a Marie Curie ITN project targetting approximate computing. It is led by Prof. Jari Nurmi at Tampere University of Technology, Finland. KTH’s role in this project is to develop a suite of approximate computing benchmarks and enhance the SiLago design framework for approximate computing.


StorAIge is an ECSEL project, led by ST Microelectronics. KTH is part of the Swedish consortium along with Uppsala University, Atlas Copco and Strikersoft. The Swedish consortium’s role in StorAIge is to implement two challenging edge-AI applications from Atlas Copco and Strikersoft in the SiLago platform.

The Atlas Copco use case is to enhance their tighetening tools so that the operator tightens all the bolts in the right sequence and with right tightening program. Knowing the right tightening program requires identification of the precise location of the bolt.

The Strikersoft use case is to enhance their tablet based SwipeCare product line with edge AI as a decision support system. In this project, the plan to implement anomaly detection for three medical conditions: Sepsis, ECG and heart arrythmia.

As the resources available in the project will not be sufficient to manufacture a chip, we will produce two implementations. A virtual silicon SiLago implementation and an FGPA based demo, integrated with sensors. The FPGA based demo will serve as proof of concept and also validate the need for a highly energy efficient SiLago implementation.


With IMEC, KTH is developing a compiler for IMEC’s propietary architecture for ML accelerators. The IMEC architecture has some similarity to KTH’s SiLago machine learning architecture has many similarities to the IMEC architecture and the high-level synthesis tool of the KTH architecture is being also for the IMEC architecture. Besides the high-level synthesis, the plan is to develop wave based computing ALUs in collaboration with IMEC.

MemBrain - VR

BCPNN (Bayesian Confidence Propagation Neural Network) is a biologically plausible model of cortex. A human scale network requires 176 TFlops/s, 50 TBs of synaptic storage, 200 TBs/s bandwidth to synaptic storage, and 50 GB/s spiking bandwidth. The group has long experience in mapping BCPNN to ASIC style implementation with custom 3D integrated DRAM. However, inspite of customization and many clever optimization, power consumption is dominated by the synaptic storage and access to it. This is the direct manifestation of the Von Neumann bottleneck. To fundamentally eliminate the Von Neumann bottleneck, we need to fuse the storage and memory together. Computation in memristors offer, one such possibility. In this project, together with our collaborators in Fudan, we are mapping BCPNN to a crossbar of memristors. A paper describing this work has been published in Frontiers. In the next steps, we plan to evaluate how robust BCPNN is to the variance in memristor devices in space and in time. This will be followed by factoring in the cost drive circuits and control logic in CMOS. Once complete, we will know to what extent computation in memristors can overcome the Von Neumann bottleneck. Our preliminary estimate is that it should be possible to reach 100 watts for a human scale realtime BCPNN and volume is also expected to be quite compact - as small as the box in which smartphones come today.