My Research topic
Design methods for scalable NoC-based architectures for the Sea-of-cores Era
Complex multimedia applications are mostly implemented on multi-core Systems on Chip. The number of cores in these systems is growing and will soon reach thousands of cores or more, i.e., we will soon be in the Sea-of-Cores era. Several problems may set barriers the development of systems. One of them is the organisation of memory hierarchies, another is how such systems should be described, a third is the efficiency of mapping applications onto a massively parallel architectures.
The emergence of multi-core systems will provide a substantial challenge in embedded system design. Not only will it give an extra dimension to compiling, with the possibility to parallelize and deploy functionality at computational nodes, but the interconnect network will need to handle communication latency while ensuring quality of service. Moreover, when dealing with synchronization and debugging, there will often be the additional problem of handling different clock domains. Also, because of electron migration and/or deployment of the device in a hostile environment (space probes, nuclear power plants etc.), these system will degrade over time. Thus, dynamic re-allocation of computational tasks and fault-tolerance on the architectural level, will ensure a pro-longed life-time by enabling graceful shutdown of the systems.
This project aims at developing a design methodology for designing and mapping applications onto Infinitely Scalable Sea-of-Cores sized Network-on-Chips (>1000 nodes/chip).
Motivation and Problem formulation (goals):
The emergence of multi-core systems will provide a substantial challenge in embedded system design. Not only will it give an extra dimension to compiling, with the possibility to parallelize and deploy functionality at computational nodes, but the interconnect network will need to handle communication latency while ensuring quality of service. Moreover, when dealing with synchronization and debugging, there will often be the additional problem of handling different clock domains. Also, because of electron migration and/or deployment of the device in a hostile environment (space probes, nuclear power plants etc.), these system will degrade over time. Thus, dynamic re-allocation of computational tasks and fault-tolerance on the architectural level, will ensure a pro-longed life-time by enabling graceful shutdown of the systems.
This project aims at developing a design methodology for designing and mapping applications onto Infinitely Scalable Sea-of-Cores sized Network-on-Chips (>1000 nodes/chip).
Motivation and Problem formulation (goals):
- How to do build and clock infinitely scalable NoCs (is-NoCs).
- How to handle mapping of tasks for infinitely scalable NoCs.
- How to build an OS that supports fault-tolerance and remapping of tasks for is-NoCs.
- How to deal with configuration & program maintenance of CPU nodes in a "Sea-of-Cores (SoC)" situation.