Royal Institute of Technology,

School of Information and Communication Technology,

Department of Industrial and Medical Electronics



Awet Yemane Weldezion

Researcher at KTH-ICT-IME


Visiting address


Isafjordsgatan 26, 3rd floor, Lift B 

Office:+46 8 790 41 97


Mailing Address:

Electrum 229 
SE-164 40 Kista 


Google Map Address



Dr. Awet Yemane Weldezion is a researcher in Electronic Systems Design at KTH - Royal Institute of Technology, Stockholm, Sweden (2008-2016). He received BSc. in Electrical and Computer Engineering from Addis Ababa University (2000), MSc. in System-on-Chip design from KTH (2006), MBA in Innovation and Growth from University of Turku – Finland (2012), and PhD in Electronic Systems Design from KTH (2016). He has industrial work experience as Applications Research Engineer focusing on microcontroller based product design, programming and implementation (2000-2004). His research interests span in areas of heterogeneous 3-D integration technology, Through Silicon Via (TSV) and On-chip networks (3D-NoC) architecture design and modeling.

Research projects:

Currently working on ‘3DNOC architecture’ with research group led by Prof. Hannu Tenhunen at KTH-ICT-IME. Involved in Horizon-2020 project Sci-GaIA, Sida funded iGrid. Previously involved in project ELITE– a consortium funded by European Union Seventh Framework Programme (7th FWP), in iPack Vinn Excellence Center funded by Vinnova - the Swedish governmental agency for innovation systems, and also in educational activities of European Institute of Technology – EIT-ICT labs.

Academic qualification:

·         PhD. in Electronic Systems Design (2016), KTH - Royal Institute of Technology, Stockholm, Sweden.

·         MBA in Innovation and Growth (2012), UTU - University of Turku, Turku, Finland.

·         MSc. in System-on-Chip (SoC) Design (2006), KTH - Royal Institute of Technology, Stockholm, Sweden

·         BSc. in Electrical & Computer Engineering (2000), AAU - Addis Ababa University, Addis Ababa, Ethiopia.


·         A.Y. Weldezion, M. Grange, A. Jantsch, H.Tenhunen, and D. Pamunuwa, “Zero-load predictive model for performance analysis in deflection routing NoCs”, Journal of ​​M​​ic​​roprocessors and Microsystems, Volume 39, Issue 8, pp. 634-647, November 2015, ISSN 0141-9331.

·         A.Y. Weldezion, M. Ebrahimi, M. Daneshtalab, and H. Tenhunen. “Automated Power and Latency Management in Heterogeneous 3D NoCs”. Eighth International Workshop on Network on Chip Architectures (NoCArc), Waikiki, Hawaii, USA, December 2015.

·         A-M. Rahmanisane, H. Tenhunen, P. Liljeberg, A.Y. Weldezion, S. Kanduru, J. Plosila, M-H Haghbayan, A. Jantsch. "Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach". In Proceedings of the International Conference on Low Power Electronics and Design, Rome, Italy, July 2015.

·         M-H. Haghbayan, A-M. Rahmani, A.Y. Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, and H. Tenhunen. Dark silicon aware power management for manycore systems under dynamic workloads. In Proceedings of the International Conference on Computer Design, Seoul, South Korea, October 2014.

·         A.Y. Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, and Hannu Tenhunen. “A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns”. In Proceedings of the 3D Systems Integration Conference (3DIC), San Francisco, California, USA, October 2013.

·         A.Y. Weldezion, R. Weerasekara, H. Tenhunen, “Design Space Exploration of Clock pumping Techniques to Reduce Through Silicon Via TSV Manufacturing Cost In 3D Integration”. in Proceedings of the 14th IEEE Electronics Packaging Technology Conference (EPTC 2012), Singapore, December 2012.

·         M. Grange, R. Weerasekera, D. Pamunuwa, A. Jantsch, and A.Y. Weldezion, "Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks". In Proceedings of the Networks on Chip Symposium (NoCS), Pittsburgh, Pennsylvania USA, May 2011.

·         A.Y. Weldezion, Z. Lu, R. Weerasekera, and H. Tenhunen, "3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture". In Proceedings of IEEE International Conference on 3D System Integration (3DIC 2009), San Francisco USA, September 2009.

·         A.Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera and H. Tenhunen. “Scalability of network-on-chip communication architecture for 3-D meshes”. In Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2009), San Diego USA, May 2009.

·         A.Y. Weldezion, R. Weerasekera, D. Pamunuwa ,L. Zheng and H. Tenhunen, ”Bandwidth Optimization for Through Silicon Via(TSV) bundles in 3D Integrated Circuits”. In 3D Integration Workshop, The Design, Automation, and Test in Europe (DATE) conference, Nice France, April 2009.

·         M. Grange, A.Y. Weldezion, D. Pamunuwa, R. Weerasekera, H. Tenhunen and D. Shippen, "Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh". In Proceeding of IEEE International Conference on 3D System Integration (3DIC 2009), San Francisco USA, September 2009.

·         W. Ahmed, L. Zheng, R. Weerasekera, Q. Chen, A.Y. Weldezion and H. Tenhunen. “Power Integrity Optimization of 3D Chips Stacked Through TSVs”. In Proceedings of the 18th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS 2009), Portland USA October 2009.


·         A.Y. Weldezion, "Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture". PhD. thesis in Electronic Systems Design. KTH-Royal Institute of Technology, Stockholm, Sweden, ISBN 978-91-7595-803-3, January 2016.

·         A.Y. Weldezion, "A Business Model for a University Based High-tech Research Center: Innovation-Centric Research Model". MBA thesis in Innovation and Growth. UTU - University of Turku, Finland. September 2012.

·        A.Y. Weldezion, "Vital Signs Acquisition and Communication System Board Implementation". MSc. thesis in System-on-Chip Design. KTH-Royal Institute of Technology, Stockholm, Sweden, November 2006.

·        A.Y. Weldezion, B.T. Asnake "Software User/Usage Licensing – using Java". BSc. thesis in Electrical and Computer Engineering. AAU-Addis Ababa University, Ethiopia, June 2000.

Industrial experience:

·         Revots PLC, Addis Ababa, 2002 - 2004,

o    Research Engineer, Co-Founder 

o    Duties: Worked in maintenance and PCB design of industrial modules and devices.

·         High Tech Park PLC, Addis Ababa, 2000 – 2002

o    Research Engineer 

o    Duties: Worked in firmware programming of 80c51 controllers based systems