Zhonghai Lu

Research

I am an associate professor leading the Dependable Autonomous Systems group at School of Information and Communication Technology (ICT), KTH. My research interests include Network-on-Chip (NoC), MPSoC Architecture and Methodology, and Networked Embedded Systems.

I serve in the TPC for the conferences: NoCS, NoC-Arc, SoCC, NPC, APPT, ASICon.

Teaching

Theses

[1] Zhonghai Lu. Design and Analysis of On-Chip Communication for Network-on-Chip Platforms. Ph.D. thesis. Royal Institute of Technology, March 2007.

[2] Zhonghai Lu. Using Wormhole switching for networks on chip: Feasibility analysis and micro-architecture adaptation. Licentiate thesis. Royal Institute of Technology, May 2005.

[3] Zhonghai Lu. Refinement of a system specification for a digital equalizer into HW and SW implementations. Master's thesis, Department of Microelectronics and Information Technology, Royal Institute of Technology, December 2001. IMIT/2001-18.

Transaction/Journal Papers

[1] Shaoteng Liu, Axel Jantsch and Zhonghai Lu. ”An Allocator for Homogeneous Resource Allocation in Network on Chip”. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Accepted for publication in September 2013.

[2] Zhi Zhang, Zhonghai Lu, Vardan Saakian, Xing Qin, Qiang Chen, and Li-Rong Zheng. "Item-level indoor localization with passive UHF RFID based on tag interaction analysis". IEEE Transactions on Industrial Electronics, 61(4):2122-2135, April 2014.

[3] Abbas Eslami Kiasari, Axel Jantsch and Zhonghai Lu. "Mathematical Formalisms for Performance Evaluation of Networks-on-Chip". ACM Computing Survey, Volume 45, Issue 3, June 2013.

[4] Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing. "Addressing Transient and Permanent Faults in NoC with Efficient Fault-tolerant Deflection Router". IEEE Transaction on Very Large Scale Integration Systems (TVLSI). vol. 21, no. 6, pp. 1053-1066, June 2013.

[5] Abdul Naeem, Axel Jantsch and Zhonghai Lu. "Scalability Analysis of Memory Consistency Models in NoC based Distributed Shared Memory SoCs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), VOL. 32, NO. 5, pp. 760-773, MAY 2013.

[6] Abbas Eslami Kiasari, Zhonghai Lu, and Axel Jantsch. "An Analytical Latency Model for Networks-on-Chip". IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.21, no.1, pp.113-123, Jan. 2013.

[7] Meikang Qiu, Zhong Ming, Jiayin Li, Shaobo Liu, Bin Wang, Zhonghai Lu. "Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors". Journal of Systems Architecture - Embedded Systems Design 58(10): 439-445, 2012.

[8] Ming Liu, Zhonghai Lu, Wolfgang Kuehn and Axel Jantsch. "A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications". International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 3(2): 23-39, 2012.

[9] Chaochao Feng, Zhonghai Lu, Axel Jantsch and Minxuan Zhang. "A 1-cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip". IEICE Transactions on Information and Systems. 95-D(5): 1519-1522, 2012.

[10] Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang and Xianju Yang. "Support Efficient and Fault-tolerant Multicast in Bufferless Network-on-Chip". IEICE Transactions on Information and Systems. 95(4):1052-1061, 2012.

[11] Wenmin Hu, Hengzhu Liu, Zhonghai Lu, Axel Jantsch, G Hu. "Self-selection pseudo-circuit: a clever crossbar pre-allocation", IEICE Electronics Express, 9(6):558-564, 2012.

[12] Wenmin Hu, Zhonghai Lu, Hengzhu Liu, Axel Jantsch. "TPSS: A Flexible Hardware Support for Unicast and Multicast on Networks-on-Chip". Journal of Computers. 7(7):1743-1752, 2012.

[13] Zhi Zhang, Zhonghai Lu, Qiang Chen, Xiaolang Yan and Li-Rong Zheng. "CDMA-PPM UWB RFID for Internet of Things: Concept and Analysis", International Journal of Communication Systems. 25(9):1103-1121, 2012.

[14] Yancang Chen, Zhonghai Lu, Lunguo Xie, Jinwen Li, Minxuan Zhang. "A single-cycle output buffered router with layered switching for Networks-on-Chips". Computers & Electrical Engineering 38(4):906-916, 2012.

[15] Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou and Li-Rong Zheng. "Performance Analysis of Flow Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks". International Journal of Distributed Sensor Networks (IJDSN). 2012.

[16] Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen and H Gu. "Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property", Computers & Electrical Engineering, 2012.

[17] Zhi Zhang, Zhonghai Lu, Qiang Chen and Xiaolang Yan, "Design and Optimization of a CDMA-based Multi-Reader Passive UHF RFID System for Dense Scenarios," IEICE Transactions on Communications, Vol.E95-B, No.01, pp.206-216, Jan. 2012.

[18] Xiaowen Chen, Shuming Chen, Zhonghai Lu, Axel Jantsch: "Hybrid Distributed Shared Memory Space in Multi-core Processors". Journal of Software (JSW) 6(12): 2369-2378, Dec. 2011.

[19] Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen and Hai Liu, "Cooperative Communication Based Barrier Synchronization in On-Chip Mesh Architectures", IEICE Electronics Express, Vol.8, No.22, 1856–1862, November 2011.

[20] Ming Liu, Zhonghai Lu, Wolfgang Kuehn and Axel Jantsch. FPGA-based Particle Recognition in the HADES Experiment. IEEE Design & Test of Computers, July/August 2011.

[21] Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Zhonghai Lu, Dimitrios Soudris, and Axel Jantsch, "Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations". IEEE Embedded Systems Letters. pp. 66-69. June 2011.

[22] Ming Liu, Wolfgang Kuehn, Soeren Lange, Shuo Yang, Johannes Roskoss, Zhonghai Lu, Axel Jantsch, Qiang Wang, Hao Xu, Dapeng Jin, Zhen'an Liu. "A High-end Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments", Computing in Science and Engineering (CiSE). 13(2):52 - 63, March/April 2011.

[23] Ning Ma, Zhonghai Lu, Li-Rong Zheng: System design of full HD MVC decoding on mesh-based multicore NoCs. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 217-229, March 2011.

[24] Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad Hossein Yaghmaee. "Buffer Optimization in Network-on-Chip Through Flow Regulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 29(12), pages 1973 - 1986, December 2010.

[25] Yue Qian, Zhonghai Lu and Wenhua Dou. Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(5), pages 802 - 815, May 2010.

[26] Yue Qian, Zhonghai Lu and Wenhua Dou. "Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on "VLSI Design and CAD Algorithms", Dec. 2009.

[27] Yue Qian, Zhonghai Lu, Wenhua Dou and Qiang Dou. "Analyzing Credit-based Router-to-Router Flow Control for On-Chip Networks", IEICE Transactions on Electronics, Special Section on "Hardware and Software Technologies on Advanced Microprocessors", Oct. 2009.

[28] Zhonghai Lu and Axel Jantsch. TDM Virtual-Circuit Configuration for Network-on-Chip. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 16(8):1021-1034, August, 2008.

[29] Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng and Dian Zhou. Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor Networks, International Journal of Software Engineering and Its Applications (IJSEIA), Vol.2, No.3, July 2008.

[30] Zhonghai Lu and Axel Jantsch. Admitting and Ejecting Flits in Wormhole-switched Networks on Chip. IET Computers & Digital Techniques 1(5):546-556, September 2007.

[31] Ingo Sander, Axel Jantsch, and Zhonghai Lu. Development and application of design transformations in ForSyDe. IEE Proceedings - Computers & Digital Techniques, 5:313-320, September 2003.

Book Chapters

[1] Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch. Adaptively reconfigurable controller for the flash memory. In Book of Flash Memory. InTech, 2011. ISBN: 978-953-307-272-2.

[2] Axel Jantsch, Xiaowen Chen, Abdul Naeem, Yuang Zhang, Sandro Penolazzi, and Zhonghai Lu. Memory architecture and management in an NoC platform. In Axel Jantsch and Dimitrios Soudris, editors, Scalable Multi-core Architectures: Design Methodologies and Tools. Springer, 2011.

[3] Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrja, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, and Philippe Martin. The MOSART mapping optimization for multi-core architectures. In Designing Very Large Scale Integration Systems: Emerging Trends and Challenges. Springer, 2011.

[4] Axel Jantsch and Zhonghai Lu. Resource allocation for quality of service on-chip communication. In Fayez Gebali and Haytham Elmiligi, editors, Networks on Chip: Theory and Practice. Taylor & Francis Group LLC - CRC Press, 2009.

[5] Zhonghai Lu, Ingo Sander, and Axel Jantsch. Refining synchronous communication onto network-on-chip best-effort services. In Alain Vachoux, editor, Applications of Specification and Design Languages for SoCs. Springer, Sept. 2006.

[6] Zhonghai Lu and Raimo Haukilahti. NoC application programming interfaces. In Networks on Chip, pages 239-260. Kluwer Academic Publishers, February 2003.

Magazine and Other Articles

[1] Zhonghai Lu. "The Accurate DRAM Model". OCP-IP newsletter, July 2011.

[2] Zhonghai Lu, Axel Jantsch, Erno Salminen, and Cristian Grecu. "Using micro-benchmarks to evaluate & compare Networks-on-chip MPSoC designs". Embedded Systems Design, September 28, 2008.

[3] Zhonghai Lu, Axel Jantsch, Erno Salminen and Cristian Grecu. "Network-on-Chip Benchmarking Specification, Part II: Micro-Benchmark Specification", Version 1.0. OCP-IP, May 2008.

Refereed International Conference Papers

Year 2014

[1] Zhonghai Lu, Yuan Yao and Yuming Jiang. "Towards Stochastic Delay Bound Analysis for Network-on-Chip". In Proceedings of the Eighth ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2014), Ferrara, Italy, September 2014.

[2] Gaoming Du, Miao Li, Zhonghai Lu, Minglun Gao and Chunhua Wang. "An Analytical Model for Worst-case Reorder Buffer Size of Multi-path Minimal Routing NoCs". In Proceedings of the Eighth ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2014), Ferrara, Italy, September 2014.

[3] Mohammad Badawi, Ahmed Hemani and Zhonghai Lu. "Customizable Coarse-grained Energy-efficient Reconfigurable Packet Processing Architecture". In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'2014), Zurich, Switzerland, June 18-20, 2014, .

[4] Yanchen Long, Zhonghai Lu, and Xiaolang Yan. "Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models". In Proceedings of Design, Automation and Test in Europe Conference (DATE'2014), Dresden, Germany, March 2014.

[5] Shaoteng Liu, Axel Jantsch and Zhonghai Lu. "Parallel Probe Based Dy namic Connection Setup in TDM NoCs". In Proceedings of Design, Automation and Test in Europe Conference (DATE'2014), Dresden, Germany, March 2014.

[6] Xueqian Zhao and Zhonghai Lu. "Empowering Study of Delay Bound Tightness with Simulated Annealing", In Proceedings of Design, Automation and Test in Europe Conference (DATE'2014), Dresden, Germany, March 2014.

[7] Yuan Yao and Zhonghai Lu. "Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems", ASP-DAC 2014: 343-348.

Year 2013

[1] Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, and Axel Jantsch. Efficient distributed memory management in a multi-core H.264 decoder on FPGA. In Proceedings of the International Symposium on System on Chip, Tampere, Finland, October 2013.

[2] Shaoteng Liu, Axel Jantsch, and Zhonghai Lu. Analysis and evaluation of circuit switched NoC and packet switch NoC. In Proceedings of Euromicro Digital System Design Conference, Santander, Spain, September 2013.

[3] Xueqian Zhao and Zhonghai Lu. "PER-FLOW DELAY BOUND ANALYSIS BASED ON A FORMALIZED MICROARCHITECTURAL MODEL", In Proceedings of the Seventh ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2013), Tempe Arizona, USA, April 2013. (Best paper candidate)

Year 2012

[1] Gaoming Du, Cunqiang Zhang, Zhonghai Lu, Alberto Saggio and Minglun Gao. “Worst-case Performance Analysis of 2-D Mesh NoCs using Multi-path Minimal Routing”. Proceedings of CODES+ISSS, Tampere, Finland, Oct. 2012.

[2] Huimin She, Zhonghai Lu and Axel Jantsch. "System-level evaluation of sensor network's deployment strategies: Coverage, lifetime and cost". In Proc. of the 8th International Wireless Communications & Mobile Computing Conference (IWCMC)", page 549-554, Cyprus, August 2012.

[3] Abdul Naeem, Axel Jantsch and Zhonghai Lu. "Architecture Support and Comparison of Three Memory Consistency Models in NoC based Systems", Proc. of Euromicro Conference on Digital Systems Design (DSD'12), 2012.

[4] Pierre Schamberger, Zhonghai Lu, Xianyang Jiang and Meikang Qiu. "Modeling and Power Evaluation of On-Chip Router Components in Spintronics", In Proceedings of the Sixth ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2012), Copenhagen, Denmark, May 2012.

[5] Zhonghai Lu and Yi Wang. "Dynamic Flow Regulation for IP Integration on Network-on-Chip", In Proceedings of the Sixth ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2012), Copenhagen, Denmark, May 2012.

[6] Shaoteng Liu, Axel Jantsch and Zhonghai Lu, "Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC", In Proceedings of Design, Automation and Test in Europe Conference (DATE'12), Dresden, Germany, March 2012.

[7] Fahimeh Jafari, Axel Jantsch and Zhonghai Lu, "Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling", In Proceedings of Design, Automation and Test in Europe Conference (DATE'12), Dresden, Germany, March 2012.

Year 2011

[1] Hai Su, Meikang Qiu, Huimin Chen, Zhonghai Lu, and Xiao Qin. "Jamming-Resilient Multi-Radio Multi-Channel Multihop Wireless Network for Smart Grid". In Proceedings of the 7th ACM Annual Cyber Security and Information Intelligence Research Workshop (CSIIR'11), Oak Ridge, Tennessee, USA. October 12 - 14, 2011.

[2] Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, and Minxuan Zhang. "Evaluation of deflection routing on various NoC topologies". In Proceedings of the IEEE International Conference on ASIC (ASICON'11), Xiamen, China, October 2011.

[3] Fahimeh Jafari, Axel Jantsch, and Zhonghai Lu. "Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling". In Proceedings of the International Conference on Computer Design (ICCD'11), Amherst, Massachusetts, USA, October 2011.

[4] Wenmin Hu, Zhonghai Lu, Axel Jantsch and Zhenan Liu, Botao Zhang, and Dongpei Liu. "Network-on-Chip Multicasting with Low Latency Path Setup". In Proceedings of the 2011 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'11). Hongkong, China, October 2011.

[5] Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng. "Stochastic Coverage in Event-Driven Sensor Networks". In Proceedings of 22nd Personal Indoor and Mobile Radio Communications (PIMRC'11), Toronto, Canada, September 2011.

[6] Abdul Naeem, Axel Jantsch, Xiaowen Chen and Zhonghai Lu. "Realization and Scalability of Release and Protected Release Consistency Models in NoC based System". In Proceedings of 14th Euromicro Conference on Digital System Design (DSD'11). Oulu, Finland. September 2011.

[7] Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Jinwen Li, and Jiang Jiang. "A low-overhead fault-aware deflection routing algorithm for 3D network-on-chip". In Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI'11), Chennai, India, July 2011.

[8] Zhonghai Lu. "Cross Clock-Domain TDM Virtual Circuits for Networks on Chips", In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip (NoCS'2011), Pittsburgh, Pennsylvania, USA, May, 2011.

[9] Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch, "FPGA-based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments", In Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC'11), Belfast, United Kingdom, March 23-25, 2011.

[10] Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou and Li-Rong Zheng. "Modeling and Analysis of Rayleigh Fading Channels using Stochastic Network Calculus," Proceedings of the IEEE Wireless Communications and Networking Conference (WCNC 2011), Cancun, Mexico, March 28-31, 2011.

[11] Wenmin Hu, Zhonghai Lu, Axel Jantsch, and Hengzhu Liu. "Power-efficient Tree-based Multicast Support for Networks-on-Chip". Proceedings of 16th Asia and South Pacific Design Automation Conference (ASPDAC'11). Yokohama, Japan, Jan. 25-28, 2011.

[12] Abdul Naeem, Xiaowen Chen, Zhonghai Lu, and Axel Jantsch. "Realization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems". Proceedings of 16th Asia and South Pacific Design Automation Conference (ASPDAC'11). Yokohama, Japan, Jan. 25-28, 2011.

Year 2010

[1] Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen. "Run-time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips". The 3rd IEEE International Symposium on Parallel Architectures, Algorithms and Programming (PAAP’2010). Dalian, China. December 18-20, 2010.

[2] Zhi Zhang, Zhonghai Lu, Qiang Chen, Xiaolang Yan, Li-Rong Zheng, "COSMO: CO-Simulation with MATLAB and OMNeT++ for Indoor Wireless Networks", The 53rd IEEE Global Telecommunications Conference (GLOBECOM 2010), Miami, USA, December 6-10, 2010.

[3] Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li and Minxuan Zhang. "A Reconfigurable Fault-tolerant Deflection Routing Algorithm Based on Reinforcement Learning for Network-on-Chip". The 3rd International Workshop on Network-on-Chip Architectures (NoCArc 2010), colocated with the 43rd Micro Conference, Dec. 4, Atlanta, USA.

[4] Abbas Eslami Kiasari, Axel Jantsch and Zhonghai Lu. "A Framework for Designing Congestion-Aware Deterministic Routing". The 3rd International Workshop on Network-on-Chip Architectures (NoCArc 2010), colocated with the 43rd Micro Conference, Dec. 4, Atlanta, USA.

[5] Xiaowen Chen, Shuming Chen, Zhonghai Lu, and Axel Jantsch. “Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier Synchronization Mechanism”. The IEEE 28th NorChip Conference. Tempere Finland. Nov. 15-16, 2010.

[6] Xiaowen Chen, Shuming Chen, Zhonghai Lu, and Axel Jantsch. "Area and Performance Optimization of Barrier Synchronization on Multi-core Network-on-Chips". In the 3rd IEEE International Conference on Computer and Electrical Engineering (ICCEE'10), Chengdu, China, November, 2010.

[7] Yue Qian, Zhonghai Lu, and Qiang Dou."QoS Scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin". The 28th International Conference on Computer Design (ICCD'10), Amerstedam, the Netherlands, Oct. 3-6, 2010.

[8] Xiaowen Chen, Zhonghai Lu, Axel Jantsch and Shuming Chen. "Handling Shared Variable Synchronization in Multi-core Network-on-Chip with Distributed Memory", The 23rd IEEE International SoC Conference (SoCC'10), Las Vegas, USA, Sept. 27-29, 2010.

[9] Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li and Minxuan Zhang, "FoN: Fault-on-Neighbor Aware Routing Algorithm for Networks-on-Chip", In Proceedings of the 23rd IEEE International SoC Conference (SOCC'10), Las Vagas, USA, September 27-29, 2010.

[10] Ning Ma, Zhonghai Lu, Zhibo Pang and Lirong Zheng. "System-Level Exploration of Mesh-based NoC Architectures for Multimedia Applications", In Proceedings of the 23rd IEEE International SoC Conference (SOCC'10), Las Vagas, USA, September 27-29, 2010.

[11] Zhi Zhang, Zhonghai Lu, Zhibo Pang, Qiang Chen, Xiaolang Yan, Li-Rong Zheng. "A Low Delay Multi-Reader Passive RFID System using Orthogonal TH-PPM IR-UWB", The 19th International Conference on Computer Communications and Networks (ICCCN'10), Zurich, Switzerland, August 25, 2010.

[12] Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch. "Inter-Process Communications using Pipes in FPGA-based Adaptive Computing", In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'10), Lixouri Kefalonia, Greece, July 2010.

[13] Xiaowen Chen, Zhonghai Lu, Axel Jantsch and Shuming Chen, "Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique", In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'10), Lixouri Kefalonia, Greece, July 2010.

[14] Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrja, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, and Philippe Martin. "Mapping optimisation for scalable multi-core architecture: The MOSART approach". In Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI'10), Lixouri Kefalonia, Greece, July 2010.

[15] Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch. "Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations", In Proceedings of the International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC'10), Karlsruhe, Germany, May 2010.

[16] Abdul Naeem, Xiaowen Chen, Zhonghai Lu and Axel Jantsch. Scalability of Weak Consistency in NoC Based Multicore Architectures. In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'10), Paris, France, May 30 - June 2, 2010.

[17] Xiaowen Chen, Zhonghai Lu, Axel Jantsch and Shuming Chen, "Supporting Distributed Shared Memory on Multi-core Network-on-Chips Using a Dual Microcoded Controller", In Proceedings of the 2010 Design, Automation and Test in Europe Conference (DATE'10), Dresden, Germany, March 2010.

[18] Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch, "FPGA-based Adaptive Computing Framework for Correlated Multi-stream Processing", In Proceedings of the 2010 Design, Automation and Test in Europe Conference (DATE'10), Dresden, Germany, March 2010.

[19] Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad H. Yaghmaee, "Optimal Regulation of Traffic Flows in Networks-on-Chip", In Proceedings of the 2010 Design, Automation and Test in Europe Conference (DATE'10), Dresden, Germany, March 2010.

Year 2009

[1] Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, and Axel Jantsch, "A Reconfigurable Design Framework for FPGA Adaptive Computing", In Proceedings of the International Conference on ReConFigurable Computing and FPGAs 2009 (ReConFig'09), Cancun, Mexico, Dec. 2009.

[2] Yue Qian, Zhonghai Lu and Wenhua Dou, "From 2D to 3D NoCs: A Case Study on Worst-Case Communication Performance", IEEE/ACM 2009 International Conference on Computer-Aided Design (ICCAD'09), San Jose, CA, Nov. 2-5, 2009. (Best paper candidate)

[3] Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen. Speedup analysis of data-parallel applications on multi-core NoCs. In Proceedings of the IEEE International Conference on ASIC (ASICON'09), Changsha, China, October 2009.

[4] Zhonghai Lu and Axel Jantsch. Trends of terascale computing chips in the next ten years. In Proceedings of IEEE ASICON 2009, ChangSha, China, October 2009. (Invited paper)

[5] Yue Qian, Zhonghai Lu and Wenhua Dou, "Applying Network Calculus for Performance Analysis of Self-Similar Traffic in On-Chip Networks", IEEE/ACM/IFIP 2009 International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS'09), Grenoble, France, Oct. 11-16, 2009.

[6] Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, and Hannu Tenhunen. "3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture", IEEE International 3D System Integration Conference, San Francisco, CA, USA, September 28-30, 2009.

[7] Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch and Dave Shippen. "Physical mapping and performance study of a multi-clock 3-Dimensional network-on-chip mesh", IEEE International 3D System Integration Conference, San Francisco, CA, USA, September 28-30, 2009.

[8] Zhonghai Lu, Dimitris Brachos and Axel Jantsch, "A Flow Regulator for On-Chip Communication", The 22nd IEEE International SoC Conference (SoCC'09), Belfast, Northern Ireland, UK, Sept. 9-11, 2009.

[9] Ming Liu, Wolfgang Kuehn, Zhonghai Lu, and Axel Jantsch. Run-time partial reconfiguration speed investigation and architectural design space exploration. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'09), Prague, Chech Republic, September 2009.

[10] Li Tong, Zhonghai Lu and Hua Zhang, "Exploration of Slot Allocation for On-Chip TDM Virtual Circuits", The 12th EUROMICRO Conference on Digital System Design (DSD'09), Greece, Patras, August 27-29, 2009.

[11] Yue Qian, Zhonghai Lu, Wenhua Dou. Analysis of Worst-case Delay Bounds for Best-effort Communication in Wormhole Networks on Chip. Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09), San Diego, CA, May 2009.

[12] Ming Liu, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes Lang, Lu Li, Soeren Lange, Zhen'an Liu, Zhonghai Lu, David Muenchow, Vladimir Pechenov, Johannes Roskoss, Stephano Spataro, Qiang Wang, and Hao Xu. Trigger algorithm development on fpga-based compute nodes. In 16th IEEE NPSS Real Time Conference, Beijing, May 2009.

[13] Qiang Wang, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes Lang, Soeren Lange, Lu Li, Ming Liu, Zhen'an Liu, Zhonghai Lu, David Muenchow, Johannes Roskoss, and Hao Xu. Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering. In 16th IEEE NPSS Real Time Conference, Beijing, May 2009.

[14] Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen. Scalability of Network-on-Chip Communication Architecture for 3-D Meshes. Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09), San Diego, CA, May 2009.

[15] Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair Bruce, Pieter van der Wolf and Tomas Henriksson. "Flow Regulation for On-Chip Communication". Proceedings of the 2009 Design, Automation and Test in Europe Conference (DATE'09), Nice, France, April 2009.

[16] Yue Qian, Zhonghai Lu and Wenhua Dou. Applying Network Calculus for Worst-case Delay Bound Analysis in On-chip Networks. Proceedings of the 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'09). Cairo, Egypt, April 2009.

[17] Yuang Zhang, Zhonghai Lu, Axel Jantsch, Li Li and Minglun Gao. Towards Hierarchical Cluster based Cache Coherence for Large-Scale Network-on-Chip. Proceedings of the 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'09). Cairo, Egypt, April 2009.

[18] Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou and Li-Rong Zheng. "Analytical evaluation of retransmision schemes in wireless sensor networks," Proceedings of the IEEE 69th Vehicular Technology Conference (VTC'09-Spring), Barcelona, Spain, April 2009.

[19] Yue Qian, Zhonghai Lu and Wenhua Dou. Comparative Analysis of Worst-Case Communication Delay Bounds for 2D and 3D NoCs. In ``Workshop on 3D Integration and Interconnect-Centric Architectures'' held in conjunction with ``International Symposium on High-Performance Computer Architecture 2009 (HPCA-15)'', Raleigh, North Carolina, USA, Feb., 2009.

[20] Yue Qian, Zhonghai Lu and Wenhua Dou. Analysis of Communication Delay Bounds for Network on Chips. Proceedings of 14th Asia and South Pacific Design Automation Conference (ASPDAC'09). Yokohama Japan, Jan. 2009.

Year 2008

[1] Yu Wang, Kai Zhou, Zhonghai Lu and Huazhong Yang, "Dynamic TDM Virtual Circuit Implementation for NoCs", Proceedings of Asia-Pacific Conference on Circuits and Systems (APCCAS'08), Macao China, Dec. 2008.

[2] Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhenan Liu, Zhonghai Lu, and Axel Jantsch. ATCA-based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments. In Proceedings of the International Conference on Field Programmable Logic and Applications 2008 (FPL'08), Heidelberg, Germany, Sept. 2008.

[3] Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch. System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments. In Proceedings of the 11th EUROMICRO Conference on Digital System Design (DSD'08), Parma, Italy, Sept. 2008.

[4] Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng and Dian Zhou. Deterministic Worst-case Performance Analysis for Wireless Sensor Networks. Proceedings of the 2008 International Conference on Wireless Communications and Mobile Computing Conference (IWCMC'08), Greece, Aug. 6-8, 2008.

[5] Zhonghai Lu, Lei Xia, Axel Jantsch. Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. In Proceedings of the 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits Systems (DDECS'08), Bratislava, Slovakia, April 16-18, 2008.

Year 2002 - 2007

[1] Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez and Zhenan Liu. Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics. In Proceedings of the 2007 International Conference on Field Programmable Technology (ICFPT'07), Japan, Dec. 12-14, 2007.

[2] Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng and Dian Zhou. Traffic Splitting with Network Calculus for Mesh Sensor Networks. In Proceedings of the 2007 International Workshop on Wireless Ad Hoc, Mesh and Sensor Networks (WAMSNet-07), Korea, Dec. 6-8, 2007.

[3] Zhonghai Lu and Axel Jantsch. Slot Allocation for TDM Virtual-Circuit Configuration for Network-on-Chip. In Proceedings of the 2007 International Conference on Computer-Aided Design (ICCAD'07), San Jose, CA, USA, Nov. 2007.

[4] Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng and Dian Zhou. A Network-based System Architecture for Remote Medical Applications. In Asia-Pacific Advanced Network (APAN'07), Xian, China, Aug. 2007.

[5] Zhonghai Lu, Ming Liu, and Axel Jantsch. Layered Switching for Networks on Chip. In Proceedings of the 44th Design Automation Conference (DAC'07), San Diego, CA, USA, June 2007.

[6] Zhonghai Lu, Jonas Sicking, Ingo Sander, and Axel Jantsch. Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. In Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP'07), Porto Alegre, Brazil, May 2007.

[7] Zhonghai Lu, Ingo Sander, and Axel Jantsch. Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication. In Proceedings of the 9th Euromicro Conference on Digital System Design (DSD'06), Dubrovnik, Croatia, August 2006.

[8] Zhonghai Lu, Mingchen Zhong, and Axel Jantsch. Evaluation of on-chip networks using deflection routing. In Proceedings of the 16th ACM Great Lakes Symposium on VLSI (GLSVLSI'06), Philadelphia, USA, May 2006.

[9] Zhonghai Lu, Bei Yin, and Axel Jantsch. Connection-oriented multicasting in wormhole-switched networks on chip. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'06), Karlsruhe Germany, March 2006.

[10] Zhonghai Lu, Ingo Sander, and Axel Jantsch. Refinement of a perfectly synchronous communication model onto Nostrum NoC best-effort communication service. In Proceedings of the Forum on Specification and Design Languages (FDL'05), Lausanne, Switzerland, September 2005.

[11] Zhonghai Lu, Li Tong, Bei Yin, and Axel Jantsch. A power-efficient flit-admission scheme for wormhole-switched networks on chip. In Proceedings of the 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, USA, July 2005.

[12] Zhonghai Lu and Axel Jantsch. Traffic configuration for evaluating networks on chips. In Proceedings of the 5th International Workshop on System on Chip (IWSOC'05), Banff, Canada, July 2005.

[13] Zhonghai Lu, Rikard Thid, Mikael Millberg, Erland Nilsson, and Axel Jantsch. NNSE: Nostrum network-on-chip simulation environment. In DATE 2005 University Booth Tool Demonstration, Munich, Germany, March 2005.

[14] Zhonghai Lu, Axel Jantsch, and Ingo Sander. Feasibility analysis of messages for on-chip networks using wormhole routing. In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC'05), Shanghai, China, January 2005.

[15] Zhonghai Lu and Axel Jantsch. Flit admission in on-chip wormhole-switched networks with virtual channels. In Proceedings of the International Symposium on System-on-Chip (ISSoC'04), Tampere, Finland, November 2004.

[16] Zhonghai Lu and Axel Jantsch. Flit ejection in on-chip wormhole-switched networks with virtual channels. In Proceedings of the IEEE NorChip Conference (Norchip'04), Oslo, Norway, November 2004.

[17] Ingo Sander, Axel Jantsch, and Zhonghai Lu. Development and application of design transformations in ForSyDe. In Design, Automation and Test in Europe Conference (DATE'03), Munich, Germany, March 2003. (Best paper nomination)

[18] Zhonghai Lu, Ingo Sander, and Axel Jantsch. A case study of hardware and software synthesis in ForSyDe. In Proceedings of the 15th International Symposium on System Synthesis (ISSS'02), Kyoto, Japan, October 2002.

Research Visit

[1] Swiss Federal Institute of Technology Zurich (ZTHz), Switzerland. Nov. 2009 - Jan. 2010. Performance Analysis and Realtime Embedded Systems.

[2] Fudan University, Nanjing University and National University of Defense Technology, China. June - July 2009. Terascale computing architectures.

[3] National Institute of Informatics, Tokyo, Japan, Oct. - Nov. 2008. Quality-of-Service control in wireless sensor networks.

[4] Samsung Electronics, Seoul Korea, June - August 2005. A Comparative Study on the State-of-the-art System-on-Chip (SoC) Architectures.

[5] Tempere University of Technology, Finland. June 2004. Network-on chip Architectures.

Update: 2009-08-08