Tage Mohammadat


Born 1988, in Abu Dhabi, United Arab Emirates. Graduated with a first class degree in Electrical and Electronic Engineering from Universiti Teknologi Petronas, Perak, Malaysia in 2010. Obtained a master of science degree in system-on-chip design in 2017.

Interested in R&D of embedded computing systems. Had a formal doctoral employment in 2016 at KTH Royal Institute of Technology within the school of electrical engineering and computer science.

Skills and Expertise

Research and Developement
Embedded Systems Design - Hardware
Embedded Systems Developement - Software
Organisational, Management and Leadership Skills

Experience and commission-of-trusts

2016 - Present

Doctoral Researcher

KTH Royal Institute of Technology

Vice ordförande, 2018/19

Doktorandsektionen, Tekniska Högskolans Studentkår

Ordförande, 2018/19

Doktorandkommittén, Sveriges Förenade Studentkårer

Styrelseledamot, 2019

ST inom Universitets-& Högskoleområdet, Kungliga Tekniska Högskolan

Sweden, Stockholm

2013 - 2014

Research Engineer

Telecommunication Research Center and Electricity Company

Sudan, Khartoum

2010 - 2013

Graduate/Research Assistant

Universiti Teknologi Petronas

Malaysia, Perak


2014 - 2017

System-on-Chip Design, Master Degree

KTH Royal Institute of Technology

Sweden, Stockholm

2006 - 2010

Electrical and Electronic Engineering, Bachelor Degree

Universiti Teknologi Petronas

Malaysia, Perak



Architectural Design for Multiprocessor Systems, Division of Electronics & Embedded Systems

KTH Royal Institute of Technology

Sweden, Stockholm

Design space exploration

Publication highlights:

  • Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors, co-author, DOI10.1109/DSD.2018.00011
  • Architecture for safe and power-efficient mixed-criticality systems, co-author, DOI: 10.1016/j.micpro.2017.05.016
  • 2010-2012

    Resistive opens testing in nanometric digital ICs, Department of Electrical and Electronic Engineering

    Universiti Teknologi Petronas

    Malaysia, Perak

    Modelling and testing resistive open faults in nanometric digital ICs

    Publication highlights:

    Multivoltage Aware Resistive Open Fault Model, IEEE transaction on VLSI, main author, DOI: 10.1109/TVLSI.2013.2243926 

    Resistive open faults detectability and implication on IC testing, IEEE transaction on VLSI-brief, main author, DOI: 10.1109/TVLSI.2014.2312357


    Electronic design automation (EDA), embedded systems, formal system design (ForSyDe), hardware-software co-design, design space exploration (DSE), real-time systems, safety-critical applications, mixed-criticality systems.



    Philosophy of knowledge, values and existence played a crucial role of my self-developement and actualisation.

    Sport and leisure

    Gym, running, swimming, climbing, kayaking, hiking, chess.

    Humanitarian causes

    Health, education, human rights

    Work Address

    Department of Electronics,
    Electrum 229, Kistagången 16,
    School of Electrical Engineering and Computer Science,
    KTH Royal Institute of Technology,
    164 40 Kista, Stockholm, Sweden
    Tage M @ KTH . SE