@inproceedings{attarzadeh_niaki_design_2008,
address = {Atlanta, {GA}, {USA}},
title = {Design space exploration for field programmable compressor trees},
isbn = {978-1-60558-469-0},
url = {http://portal.acm.org/citation.cfm?id=1450095.1450126},
doi = {10.1145/1450095.1450126},
abstract = {The Field Programmable Compressor Tree {(FPCT)} is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an {FPGA} or other reconfigurable device. This paper presents a design space exploration {(DSE)} method that can be used to identify the best {FPCT} architecture for a given set of arithmetic benchmark circuits; in practice, an {FPGA} vendor can use the design space exploration to tailor the {FPCT} to meet the needs of the most important benchmark circuits of the vendor's largest-volume clients. One novel feature of the {DSE} is the introduction of a metric called {I/O} utilization; we found that {I/O} utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using {I/O} utilization allowed us to reduce significantly the number of {FPCTs} that must be synthesized and evaluated during the {DSE}, while giving high confidence that the best architectures are still explored. The {DSE} was applied to seven small-to-medium range benchmark circuits; one {FPCT} architecture was found that was 30\% faster than the second best in terms of critical path delay, and only 3.34\% larger than the smallest.},
booktitle = {Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems},
publisher = {{ACM}},
author = {Attarzadeh Niaki, Seyed Hosein and Cevrero, Alessandro and Brisk, Philip and Nicopoulos, Chrysostomos and Gurkaynak, Frank K. and Leblebici, Yusuf and Ienne, Paolo},
year = {2008},
keywords = {design space exploration (dse), field programmable compressor tree (fpct)},
pages = {207--216}
}
@article{cevrero_field_2009,
title = {Field Programmable Compressor Trees: Acceleration of {Multi-Input} Addition on {FPGAs}},
volume = {2},
shorttitle = {Field Programmable Compressor Trees},
url = {http://portal.acm.org/citation.cfm?id=1534923},
doi = {10.1145/1534916.1534923},
abstract = {Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The {DSP} blocks embedded in high-performance {FPGAs} perform fixed bitwidth parallel multiplication and {Multiply-ACcumulate} {(MAC)} operations. In theory, the compressor trees contained within the multipliers could implement multi-input addition; however, they are not exposed to the programmer. To improve {FPGA} performance for these applications, this article introduces the Field Programmable Compressor Tree {(FPCT)} as an alternative to the {DSP} blocks. By providing just a compressor tree, the {FPCT} can perform multi-input addition along with parallel multiplication and {MAC} in conjunction with a small amount of {FPGA} general logic. Furthermore, the user can configure the {FPCT} to precisely match the bitwidths of the operands being summed. Although an {FPCT} cannot beat the performance of a well-designed {ASIC} compressor tree of fixed bitwidth, for example, 9×9 and 18×18-bit {multipliers/MACs} in {DSP} blocks, its configurable bitwidth and ability to perform multi-input addition is ideal for reconfigurable devices that are used across a variety of applications.},
number = {2},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
author = {Cevrero, Alessandro and Athanasopoulos, Panagiotis and {Parandeh-Afshar}, Hadi and Verma, Ajay K. and Attarzadeh Niaki, Seyed Hosein and Nicopoulos, Chrysostomos and Gurkaynak, Frank K. and Brisk, Philip and Leblebici, Yusuf and Ienne, Paolo},
year = {2009},
keywords = {compressor tree, field programmable compressor tree (fpct), field programmable gate array (fpga)},
pages = {1--36}
}
@mastersthesis{attarzadeh_niaki_design_2008-1,
title = {Design Space Exploration Of Field Programmable Counter Arrays And Their Integration With {FPGAs}},
url = {http://web.it.kth.se/~axel/papers/2008/MSc-seyed-h-a-niaki.pdf},
school = {Royal Institute of Technology {(KTH)}},
author = {Attarzadeh Niaki, Seyed Hosein},
year = {2008}
}
@inproceedings{nourian_parallel_2006,
address = {Amir Kabir Univ. of Technology, Tehran, Iran},
title = {Parallel implementation of Multi Layer Perceptron on a Linux cluster},
booktitle = {Proc. 14th Iranian Conf. Elect. Eng. {(ICEE} '06)},
author = {Nourian, Morteza and Attarzadeh Niaki, Seyed Hosein and Ilati, Hesamed'din},
month = may,
year = {2006}
}
@inproceedings{attarzadeh_niaki_co-simulation_2011,
title = {Co-simulation of embedded systems in a heterogeneous {MoC-based} modeling framework},
isbn = {978-1-61284-818-1},
doi = {10.1109/SIES.2011.5953667},
abstract = {New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code and {IP} models in order to be accepted in the industry. To tackle this problem, we introduce the concept of wrappers in the context of a formal heterogeneous embedded system modeling framework. The formalism is based on the language-independent concept of models of computation. Wrappers enable the framework to co-simulate/co-execute with external models which might be legacy code, an {IP} block, or an implementation of a partially refined system. They are defined formally in order to keep the analyzability of the original framework and also enable automations such as generation of model wrappers and co-simulation interfaces. As a proof of concept, three wrappers for models in different abstraction levels are introduced and implemented for two case studies.},
booktitle = {2011 6th {IEEE} International Symposium on Industrial Embedded Systems {(SIES)}},
publisher = {{IEEE}},
author = {Attarzadeh Niaki, Seyed Hosein and Sander, Ingo},
month = jun,
year = {2011},
keywords = {Adaptation models, Computational modeling, Computer architecture, embedded systems, Engines, Semantics, synchronization},
pages = {238--247}
}
@inproceedings{attarzadeh_niaki_semi-formal_2011,
title = {Semi-formal refinement of heterogeneous embedded systems by foreign model integration},
isbn = {978-1-4577-0763-6},
abstract = {There is a need for integration of external models in high-level system design flows. We introduce a set of partial refinement operations to implement models of heterogeneous embedded systems. The models are in form of process networks where each process belongs to a single model of computation. A semi-formal design flow has been introduced based on these operations to incrementally refine system specifications to their implementation. Wrapper processes, which allow co-simulation of a system model in the framework with external models and implementations are used to keep the intermediate system models after each refinement step verifiable. Additionally, this design flow has the advantage of integrating legacy code and {IP} cores. Using a simple example as the case study, we have shown how we can apply this design methodology to a simple system.},
booktitle = {2011 Forum on Specification and Design Languages {(FDL)}},
publisher = {{IEEE}},
author = {Attarzadeh Niaki, Seyed Hosein and Sander, Ingo},
month = sep,
year = {2011},
pages = {1--8}
}
@inproceedings{koefoed_jakobsen_system_2012,
address = {Nuremberg, Germany},
title = {System level modelling with open source tools},
abstract = {In this paper, we present a system level design methodology which allows designers to model and analyze their systems from the early stages of the design process until nal implementation. The design methodology targets heterogeneous embedded systems and is based on a formal modeling framework, called {ForSyDe.} {ForSyDe} is available under the open Source approach, which allows small and medium enterprises {(SME)} to get easy access to advanced modeling capabilities and tools. We give an introduction to the design methodology through the system level modeling of a simple industrial use case, and we outline the basics of the underlying {ForSyDe} model.},
author = {Jakobsen, Mikkel Koefoed and Madsen, Jan and Attarzadeh Niaki, Seyed Hosein and Sander, Ingo and Hansen, Jan},
month = feb,
year = {2012}
}
@inproceedings{attarzadeh_niaki_heterogeneous_2012,
title = {Heterogeneous System-Level Modeling for Small and Medium Enterprises},
abstract = {Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. In order to exploit the benefits of ESL, design languages and modeling frameworks should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of formal analysis and automated synthesis methods; c) executable, to detect specification bugs early in the design flow; and d) parallel, to be able to exploit the multi- and many-core platforms for simulation and implementation. However, most of the approaches to ESL design, do not support all of these properties together.
We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented in the library and allows the designer to focus on specifying the pure functional aspects. A key advantage of our approach is that the claimed formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis in the design flow.},
booktitle = {Symposium on Integrated Circuits and Systems Design {(SBCCI)}},
organization = {{IEEE}},
author = {Attarzadeh Niaki, Seyed Hosein and Beserra, Gilmar and Andersen, Nikolaj and Verdon, Mathias and Sander, Ingo},
month = sep,
year = {2012}
}
@inproceedings{attarzadeh_niaki_formal_2012,
title = {Formal heterogeneous system modeling with {SystemC}},
abstract = {Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. In order to exploit the benefits of ESL, design languages and modeling frameworks should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of formal analysis and automated synthesis methods; c) executable, to detect specification bugs early in the design flow; and d) parallel, to be able to exploit the multi- and many-core platforms for simulation and implementation. However, most of the approaches to ESL design, do not support all of these properties together.
We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented in the library and allows the designer to focus on specifying the pure functional aspects. A key advantage of our approach is that the claimed formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis in the design flow.},
booktitle = {Forum on Specification and Design Languages {(FDL)}},
organization = {{IEEE}},
author = {Attarzadeh Niaki, Seyed Hosein and Jakobsen, Mikkel Koefoed and Sulonen,Tero and Sander, Ingo},
month = sep,
year = {2012},
pages = {160--167},
issn = {1636-9874}
}
@inproceedings{beserra_integrating_2012,
title = {Integrating Virtual Platforms into a Heterogeneous {MoC}-Based Modeling Framework},
abstract = {In order to handle the increasing complexity of embedded systems, design methodologies must take into account important aspects, such as abstraction, IP-reuse and heterogeneity. System design often starts in a high abstraction level, by developing a virtual platform (VP), which is typically composed of TLM models. TLM has become very popular in the modeling of bus-based systems and currently there is an increasing availability of libraries that provide TLM IPs. Heterogeneity can be naturally captured in a framework supporting different Models of Computation (MoCs). We introduce a novel approach for integrating TLM IPs/VPs into a MoC-based modeling framework, allowing them to co-simulate heterogeneous systems. This approach allows to raise the abstraction level, enabling a more careful design space exploration before selecting a proper VP. We exemplify the potential of our approach with a case study in which a VP with a processor generated by ArchC communicates with a continuous-time model.},
booktitle = {Forum on Specification and Design Languages {(FDL)}},
organization = {{IEEE}},
author = {Beserra, Gilmar Silva and Attarzadeh Niaki, Seyed Hosein and Sander, Ingo},
month = sep,
year = {2012},
pages = {143--150},
issn = {1636-9874}
}
@inproceedings{Niaki:2013:APS:2485288.2485297,
author = {Attarzadeh Niaki, Seyed Hosein and Sander, Ingo},
title = {An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems},
abstract = {Simulation of complex embedded and cyber-physical systems requires exploitation of the computation power of available parallel architectures. Current simulation environments either do not address this parallelism or use separate models for parallel simulation and for analysis and synthesis, which might lead to model mismatches. We extend a formal modeling framework targeting heterogeneous systems with elements that enable parallel simulations. An automated flow is then proposed that starting from a serial executable specification generates an efficient MPI-based parallel simulation model by using a constraint-based method. The proposed flow generates parallel models with acceptable speedups for a representative example.},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe},
series = {DATE '13},
year = {2013},
isbn = {978-1-4503-2153-2},
location = {Grenoble, France},
pages = {27--30},
numpages = {4},
url = {http://dl.acm.org/citation.cfm?id=2485288.2485297},
acmid = {2485297},
publisher = {{EDA} Consortium},
address = {San Jose, CA, USA}
}
@inproceedings{herrera2013towards,
author = {Herrera, Fernando and Attarzadeh Niaki, Seyed Hosein and Sander, Ingo},
booktitle = {Euromicro Conference on Digital System Design (DSD)},
title = {Towards a Modelling and Design Framework for Mixed-Criticality {SoCs} and Systems-of-Systems},
year = {2013},
pages = {989--996},
abstract = {Mixed-criticality system (MCS) design is an emerging discipline, which has been identified as a core foundational concept in fields such as cyber-physical systems. The hard real-time design community has pioneered the contributions to MCS design, extending scheduling theory to consider mixed-criticalities and the impact of on-chip and off-chip communication infrastructures. However, the development of MCS design methodologies capable to provide safe and efficient solutions for complex applications and platforms in an acceptable design time demands a more interdisciplinary approach. This paper is a first step towards such an approach in the development of MCS design methodologies. The paper first identifies main design disciplines to be involved in MCS design, both at SoC and system-of-systems (SoS) scales. Then, the paper proposes a core ontology for modelling a mixed-criticality system at both SoC scale (MCSoC) and SoS scale (MCSoS). Finally, the paper introduces a set of aspects required for MCS design which have been identified as open and challenging attending the overviewed state-of-the-art.},
keywords = {Computational modeling;Embedded systems;Ontologies;Processor scheduling;Real-time systems;System-on-chip;Unified modeling language;Cyber-Physical Systems;Embedded Distributed Systems;Mixed- Criticality;Systems-of-Systems},
doi = {10.1109/DSD.2013.112},
organization = {{IEEE}}
}
@inproceedings{hosein2013rapid,
author = {Hosein Attarzadeh Niaki, Seyed and Mikulcak, Marcus and Sander, Ingo},
booktitle = {Forum on Specification Design Languages (FDL)},
title = {Rapid virtual prototyping of real-time systems using predictable platform characterizations},
year = {2013},
abstract = {Virtual prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM 2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.},
keywords = {Analytical models;Program processors;Prototypes;Real-time systems;Sockets;Space exploration;Time division multiplexing;automation;design-space exploration;predictable platforms;real-time systems;simulation;virtual prototyping},
issn = {1636-9874},
organization = {{IEEE}}
}
@techreport{Attarzadeh:2014:FCP,
author = {Attarzadeh Niaki, Seyed Hosein and Mikulcak, Marcus and Robino, Francesco and Sander, Ingo},
institution = {KTH, Electronic Systems},
pages = {18},
title = {A Framework for Characterizing Predictable Platform Templates},
series = {TRITA-ICT/ECS R},
number = {14:01},
year = {2014}
}
@incollection{Attarzadeh:2015:AGV,
year = {2015},
isbn = {978-3-319-06316-4},
booktitle = {Languages, Design Methods, and Tools for Electronic System Design},
volume = {311},
series = {Lecture Notes in Electrical Engineering},
editor = {Lou\"{e}rat, Marie-Minerve and Maehne, Torsten},
//doi = {10.1007/978-3-319-01418-0_9},
title = {Automatic Generation of Virtual Prototypes from Platform Templates},
//url = {http://dx.doi.org/10.1007/978-3-319-01418-0_9},
publisher = {Springer International Publishing},
author = {Attarzadeh Niaki, Seyed Hosein and Mikulcak, Marcus and Sander, Ingo},
//pages = {145-164},
language = {English}
}
@inproceedings{Attarzadeh:2015:ACP,
author = {Attarzadeh Niaki, Seyed Hosein and Altinel, Ekrem and Koedam, Martijn and Molnos, Anca and Sander, Ingo and Goossens, Kees},
booktitle = {Workshop on Model-Implementation Fidelity (MiFi)},
title = {A Composable and Predictable {MPSoC} Design Flow for Multiple Real-Time Applications},
year = {2015},
month = mar
}
@inproceedings{Diallo:2015:AFM,
title = {A Formal, Model-driven Design Flow for System Simulation and Multi-core Implementation},
author = {DIALLO, Papa Issa and Attarzadeh-Niaki, Seyed-Hosein and Robino, Francesco and Sander, Ingo and Champeau, Joel and \"{O}berg, Johnny},
booktitle = {Symposium on Industrial Embedded Systems {(SIES)}},
address = {Siegen, Germany},
pulisher = {{IEEE}},
year = {2015},
month = jun,
keywords = {Real-time and embedded systems}
}
@inproceedings{Attarzadeh:2015:IFM,
author = {Attarzadeh-Niaki, Seyed-Hosein and Sander, Ingo},
booktitle = {International Symposium on Computer Architecture and Digital Systems (CADS), To appear},
title = {Integrating Functional Mock-up Units into A Formal Heterogeneous System Modeling Framework},
year = {2015},
month = oct
}
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