Introduction

With the end of Dennard scaling and the impending termination of Moore's law, researchers are actively searching for alternative forms of computing to continue providing better, faster, and less power-hungry systems in the future. Today, several potential architectures are emerging to fill the widening void arising from the end of Moore's law, including radical (and intrusive) systems such as quantum- and neuromorphic computers. However, out of the many proposed architectures, perhaps none is as salient an alternative as Coarse-Grained Reconfigurable Architectures/Arrays (CGRAs).

CGRAs belong to the programmable logic device family of architectures, where the architectures aspire to provide some form of plasticity or reconfigurability. Such reconfigurability allows the silicon to be specialized towards a particular application in order to reduce data movement and improve performance and energy efficiency. Unlike their cousins, the Field-Programmable Gate Arrays (FPGAs), CGRAs provide reconfigurable Arithmetic Logic Units (ALUs) and a highly specialized yet versatile data path. This ``coarsening'' of reconfiguration allows CGRAs to achieve a significant (custom ASIC-like) reduction in power consumption and increase in operating frequency compared to FPGAs. At the same time, they remedy and overcome the expensive von Neumann (instruction-decoding) overhead that traditional general-purpose processors (CPUs) suffer from. In short, CGRAs strike a seemingly perfect balance between the reconfigurability of FPGAs and the performance of CPUs, with power-consumption characteristics closer to custom ASICs.

CGRAs have long research lineages that date back to their inception some 25 years ago (with theory dating back to the 1970s). However, they are recently garnering renewed interest and importance in High-Performance Computing (HPC). Today, we see an explosion in the number of custom-built AI-accelerators intended for use in data centers and the IoT-Edge-Cloud continuum. Many of these accelerators are CGRAs, such as those built by SambaNova or Cerebras. More importantly, there is an active and growing effort to use these AI accelerators to accelerate scientific applications on supercomputers, and many HPC centers are already including these CGRAs in their testbeds (e.g., Cerebras-1 in ORNL or EPCC).

This workshop provides a focused interdisciplinary forum for both CGRA hardware researchers and HPC/distributed computing researchers from academia or industry to come together to discuss state-of-the-art CGRA research for use in emerging HPC systems.

Important Dates

Workshop Program

CGRA4HPC 2024 will be held in conjunction with IPDPS 2024 in San Fransisco, US, on Friday, May 31st.

Call for Papers

Topics of Interest

CGRA Hardware and Architectures

• Novel high-performance CGRA architectures for use in HPC
• Energy-efficient architectures (incl. asynchronous/clockless CGRAs, power-consumption optimizations, etc.)

Hybrid Processor/CGRA Technology

• Software-programmable CGRAs (e.g., Xilinx ACAP Versal)
• Processors with a tightly interconnected CGRA subsystem
• Combination of CGRAs and other emerging post-Moore models (e.g., neuromorphic systems)

Programming Models, Compilers, and Middleware

• Parallel programming language support for programming CGRA architectures (e.g., supporting OpenMP or CUDA/HIP for programming CGRA architectures)
• Compilation strategies, algorithms, and methods for mapping computations and applications onto modern CGRA architectures
• Smart middleware and runtime systems for support of CGRAs, including multi-CGRA systems for HPC
• The use of CGRA frameworks (e.g., CGRA-ME and OpenCGRA) to generate and customize architectures

Use-Cases and Experiments

• Experience in porting scientific kernels and applications to state-of-the-art CGRAs (e.g., weather/climate codes, CFD, MD, etc.)
• Machine Learning applications and case studies, performance and power-efficiency comparisons between traditional systems (CPUs/GPUs) and CGRAs

CGRAs and Generative Artificial Intelligence

Paper Submission

Organization

CGRA4HPC Organizers

• Artur Podobas (KTH, Sweden)
• Kentaro Sano (RIKEN, Japan)
• Jason Anderson (University of Toronto, Canada)

CGRA4HPC Program Committee

• Ahmed Hemani (KTH, Sweden)
• Ahsan Javed Awan (Ericsson, Sweden)
• Boma Adhi (RIKEN, Japan)
• Cheng Tan (Microsoft, USA)
• Jens Domke (RIKEN, Japan)
• Lingli Wang (Fudan University, China)
• Markus Weinhardt (HS-Osnabrueck, Germany)
• Nakashima Yasuhiko (NAIST, Japan)
• Takuya Kojima (Univ. of Tokyo, Japan)