Introduction

With the end of Dennard scaling and the impending termination of Moore's law, researchers are actively searching for alternative forms of computing to continue providing better, faster, and less power-hungry systems in the future. Today, several potential architectures are emerging to fill the widening void arising from the end of Moore's law, including radical (and intrusive) systems such as quantum- and neuromorphic computers. However, out of the many proposed architectures, perhaps none is as salient an alternative as Coarse-Grained Reconfigurable Architectures/Arrays (CGRAs).

CGRAs belong to the programmable logic device family of architectures, where the architectures aspire to provide some form of plasticity or reconfigurability. Such reconfigurability allows the silicon to be specialized towards a particular application in order to reduce data movement and improve performance and energy efficiency. Unlike their cousins, the Field-Programmable Gate Arrays (FPGAs), CGRAs provide reconfigurable Arithmetic Logic Units (ALUs) and a highly specialized yet versatile data path. This ``coarsening'' of reconfiguration allows CGRAs to achieve a significant (custom ASIC-like) reduction in power consumption and increase in operating frequency compared to FPGAs. At the same time, they remedy and overcome the expensive von Neumann (instruction-decoding) overhead that traditional general-purpose processors (CPUs) suffer from. In short, CGRAs strike a seemingly perfect balance between the reconfigurability of FPGAs and the performance of CPUs, with power-consumption characteristics closer to custom ASICs.

CGRAs have long research lineages that date back to their inception some 25 years ago (with theory dating back to the 1970s). However, they are recently garnering renewed interest and importance in High-Performance Computing (HPC). Today, we see an explosion in the number of custom-built AI-accelerators intended for use in data centers and the IoT-Edge-Cloud continuum. Many of these accelerators are CGRAs, such as those built by SambaNova or Cerebras. More importantly, there is an active and growing effort to use these AI accelerators to accelerate scientific applications on supercomputers, and many HPC centers are already including these CGRAs in their testbeds (e.g., Cerebras-1 in ORNL or EPCC).

This workshop provides a focused interdisciplinary forum for both CGRA hardware researchers and HPC/distributed computing researchers from academia or industry to come together to discuss state-of-the-art CGRA research for use in emerging HPC systems.

Important Dates

Invited speaker: Patricia Gonzalez-Guerrero (Berkeley Lab)

Massive parallelism and extreme heterogeneity are key for the future of high-performance computing (HPC). One of the most popular execution models for parallelism involves shared-memory, with hardware-based cache-coherence mechanisms that enforce atomicity, ensuring transparent data movement and memory consistency. However, as the levels of parallelism (up to 100M cores) and heterogeneity increase, the scalability of cache coherence protocols is compromised. Hardware message queues (HMQs) might be key for practical massive parallelism and extreme heterogeneity because it offers a low-latency direct path for inter-node communication that bypasses expensive cache-coherence protocols. Contrary to general-purpose cache-coherence systems, the same HMQ mechanisms can be used for general-purpose cores such as RISCVs or kick-start computation in specialized accelerators such as Fast Fourier Transform. In this work, we propose MoSAIC, a full-stack platform to facilitate the evaluation and design space exploration of HMQs in parallel and heterogeneous architectures. Since field programmable arrays (FPGAs) provide a cost-effective testbed for hardware exploration, we aim at a lightweight, flexible architecture optimized for FPGAs, however, MOSAIC could also target chiplets or SoC/ASIC.

Patricia Gonzalez-Guerrero is a research scientist at Berkeley Lab. She earned her Ph.D. in 2019 and her M.Sc. in 2015, both from the University of Virginia in Charlottesville, VA, USA. She completed her bachelor's degree in 2008 at Pontifical Xavierian University in Bogota, Colombia. She worked as an ASIC Design and Verification Engineer at Hewlett-Packard in Costa Rica. Her research focuses on ultra-low power digital and mixed-signal circuit design for non-conventional computing paradigms aimed at reducing power and energy consumption. This includes areas such as synchronous and asynchronous stochastic computing, computing with sigma-delta streams, and race logic. Additionally, she has been exploring the use of FPGAs for the evaluation and exploration of high-performance computing and chiplet-based specialized accelerators.

Invited speaker: Andrew Schmidt (Advanced Micro Devices)

As academic, research, and industry explores different computer architectures, such as Course Grained Reconfigurable Arrays (CGRAs) and Neural Processing Units (NPUs) we will describe the AMD Ryzen AI™ platform and AMD’s NPUs. We present Riallto, an open-source exploration framework for first time users of the NPU developed by teams from the AMD Research and Advanced Development group and the AMD University Program. AMD Ryzen AI is the world’s first built-in AI engine on select x86 computers. This dedicated engine is built on the AMD XDNA™ spatial dataflow NPU architecture consisting of a tiled array of AI Engine processors and is designed to offer lower latency and better energy efficiency. Such processor arrays are also found in the Versal Adaptive SoC enabling rapid development and evaluation across heterogenous architectures. This integration optimizes efficiency by offloading specific AI processing tasks such as background blur, facial detection, and eye gaze correction, freeing up CPU and GPU cycles and enhancing system efficiency. With Ryzen AI-powered laptops or miniPCs, you can develop innovative applications and productivity solutions like Information search, summarization, transcription and so much more. Riallto lowers the barrier of entry and access to the AIEs and includes a wealth of education material via Juypter Notebooks that makes understanding and using ML accelerators in an ever-increasing heterogenous environment. We are excited to share details of the hardware and software architecture with the CGRA4HPC community and see how the technology can be leveraged by their work.

Workshop Program

CGRA4HPC 2024 will be held in conjunction with IPDPS 2024 in San Francisco, US, on Friday, May 31st.

Call for Papers

Topics of Interest

CGRA Hardware and Architectures

• Novel high-performance CGRA architectures for use in HPC
• Energy-efficient architectures (incl. asynchronous/clockless CGRAs, power-consumption optimizations, etc.)

Hybrid Processor/CGRA Technology

• Software-programmable CGRAs (e.g., Xilinx ACAP Versal)
• Processors with a tightly interconnected CGRA subsystem
• Combination of CGRAs and other emerging post-Moore models (e.g., neuromorphic systems)

Programming Models, Compilers, and Middleware

• Parallel programming language support for programming CGRA architectures (e.g., supporting OpenMP or CUDA/HIP for programming CGRA architectures)
• Compilation strategies, algorithms, and methods for mapping computations and applications onto modern CGRA architectures
• Smart middleware and runtime systems for support of CGRAs, including multi-CGRA systems for HPC
• The use of CGRA frameworks (e.g., CGRA-ME and OpenCGRA) to generate and customize architectures

Use-Cases and Experiments

• Experience in porting scientific kernels and applications to state-of-the-art CGRAs (e.g., weather/climate codes, CFD, MD, etc.)
• Machine Learning applications and case studies, performance and power-efficiency comparisons between traditional systems (CPUs/GPUs) and CGRAs

CGRAs and Generative Artificial Intelligence

Paper Submission

Organization

CGRA4HPC Organizers

• Artur Podobas (KTH, Sweden)
• Kentaro Sano (RIKEN, Japan)
• Jason Anderson (University of Toronto, Canada)

CGRA4HPC Program Committee

• Ahmed Hemani (KTH, Sweden)
• Ahsan Javed Awan (Ericsson, Sweden)
• Boma Adhi (RIKEN, Japan)
• Cheng Tan (Microsoft, USA)
• Jens Domke (RIKEN, Japan)
• Lingli Wang (Fudan University, China)
• Markus Weinhardt (HS-Osnabrueck, Germany)
• Nakashima Yasuhiko (NAIST, Japan)
• Takuya Kojima (Univ. of Tokyo, Japan)