SA-1100 Memory Map for Badge3

AddressPurposeSizeUsage
0x0000 0000Flash + Static Memory
0x0000 0000Static Bank Select 0(128 Mbyte)
1 MByte available		Flash Memory
16 bits wide
0x0800 0000Static Bank Select 1(128 Mbyte)
1 MByte available 		Static Memory SRAM
32 bits wide
0x1000 0000Static Bank Select 2(128 Mbyte)unused
0x1800 0000Static Bank Select 3(128 Mbyte)unused
0x2000 0000PCMCIA space
0x2000 0000PCMCIA Socket 0 space256 MbytesPCMCIA Interface
0x2000 0000Socket 0 I/O Space
0x2400 0000Socket 0 Reserved
0x2800 0000Socket 0 Attribute Space
0x2C00 0000Socket 0 Memory Space
0x3000 0000PCMCIA Socket 1 Space256 MbytePCMCIA Interface
0x3000 0000Socket 1 I/O Space
0x3400 0000Socket 1 Reserved
0x3800 0000Socket 1 Attribute Space
0x3C00 0000Socket 1 Memory Space
0x4000 0000Reserved
0x4000 0000..0x7FFF FFFFReserved1 Gbyte Accessing this reserved space results in a Data Abort Exception
0x8000 0000Peripheral Module Registers (1 Gbyte - Internal Registers)
Serial Port 0 USB Device Controller (UDC)
0x8000 0000UDCCR == UDC Control Register
0x8000 0004UDCAR == UDC Address Register
0x8000 0008UDCOMP == UDC OUT Max Packet Register
0x8000 000CUDCIMP == UDC IN Max Packet Register
0x8000 0010UDCCS0 == UDC Endpoint 0 Control/Status Register
0x8000 0014UDCCS1 == UDC Endpoint 1 Control/Status Register
0x8000 0018UDCCS2 == UDC Endpoint 2 Control/Status Register
0x8000 001CUDCD0 == UDC Endpoint 0 Data Register
0x8000 0020UDCWC == UDC Endpoint 0 Write Count Register
0x8000 0024Reserved
0x8000 0028UDCDR == UDC Data Register
0x8000 0028Serial port 0 UDC Transmit 0x80000A 0000
0x8000 0028UDC Receive 0x80000A 0001
0x8000 002CReserved
0x8000 0030UDCSR == UDC Status/Interrupt Register
Serial Port 1 UART
0x8001 0000UTCR0 == UART Control Register 0
0x8001 0004UTCR1 == UART Control Register 1
0x8001 0008UTCR2 == UART Control Register 2
0x8001 000CUTCR3 == UART Control Register 3
0x8001 0010Reserved
0x8001 0014UTDR === UART Data Register
0x8001 0014UART Transmit 0x804005 0100
0x8001 0014UART Receive 0x804005 0101
0x8001 0018Reserved
0x8001 001CUTSR0 == UART Status Register 0
0x8001 0020UTSR1 == UART Status Register 1
0x8001 0024..0x8001 FFFFReserved
SDLC
0x8002 0060SDCR0 == SDLC Control Register 0
0x8002 0064SDCR1 == SDLC Control Register 1
0x8002 0068SDCR2 == SDLC Control Register 2
0x8002 006CSDCR3 == SDLC Control Register 3
0x8002 0070SDCR4 == SDLC Control Register 4
0x8002 0074Reserved
0x8002 0078SDDR == SDLC Data Register
0x8002 0078Serial port 1 SDLC Transmit 0x80801E 0010
0x8002 0078SDLC Receive 0x80801E 0011
0x8002 007CReserved
0x8002 0080SDSR0 == SDLC Status Register 0
0x8002 0084SDSR1 == SDLC Status Register 1
0x8002 0088..0x8002 FFFFReserved
Serial Port 2 Infrared Communications Port (ICP) UART
0x8003 0000UTCR0 == UART Control Register 0
0x8003 0004UTCR1 == UART Control Register 1
0x8003 0008UTCR2 == UART Control Register 2
0x8003 000CUTCR3 == UART Control Register 3
0x8003 0010UTCR4 == UART Control Register 4
0x8003 0014UART Transmit 0x80C005 0110
0x8003 0014UART Receive 0x80C005 0111
0x8003 0018Reserved
0x8003 001CUTSR0 == UART Status Register 0
0x8003 0020UTSR1 == UART Status Register 1
0x8003 0024..0x8003 005CReserved
0x8004 0000high speed serial to parallel (HSSP) [for 4.0 Mbit/s]
0x8004 0060HSCR0 == HSSP Control Register 0
0x8004 0064HSCR1 == HSSP Control Register 1
0x8004 0068Reserved
0x8004 006CHSSP Transmit 0x81001B 0110
0x8004 006CHSSP Receive 0x81001B 0111
0x8004 006CHSDR == HSSP Data Register
0x8004 0070Reserved
0x8004 0074HSSR0 == HSSP Status Register 0
0x8004 0078HSSR1 == HSSP Status Register 1
0x8004 007C..0x8004 FFFFReserved
Serial Port 3 - UART
0x8005 0000UTCR0 == UART Control Register 0
0x8005 0004UTCR1 == UART Control Register 1
0x8005 0008UTCR2 == UART Control Register 2
0x8005 000CUTCR3 == UART Control Register 3
0x8005 0010Reserved
0x8005 0014UTDR == UART Data Register
0x8005 0014UART Transmit 0x814005 1000
0x8005 0014UART Receive 0x814005 1001
0x8005 0018Reserved
0x8005 001CUTSR0 == UART Status Register 0
0x8005 0020UTSR1 == UART Status Register 1
0x8005 0024..0x8005 FFFFReserved
Serial Port 4 (MPC multimedia communications port (MCP)
interface to the Philips UCB1100, UCB1200, and Crystal CS4271 codecs)
0x8006 0000MCCR0 == MCP Control Register 0
0x8006 0004Reserved
0x8006 0008MCDR0 == MCP Data Register 0
0x8006 0008MCP Transmit (audio) 0x818002 1010
0x8006 0008MCP Receive (audio) 0x818002 1011
0x8006 000CMCDR1 == MCP Data Register 1
0x8006 000CMCP Transmit (telecom) 0x818003 1100
0x8006 000CMCP Receive (telecom) 0x818003 1101
0x8006 0010MCDR2 == MCP Data Register 2
0x8006 0014Reserved
0x8006 0018MCSR == MCP Status Register
0x8006 001C..0x8006 005CReserved
0x8007 0000synchronous serial port (SSP)
0x8007 0060SSCR0 == SSP Control Register 0
0x8007 0064SSCR1 == SSP Control Register 1
0x8007 0068Reserved
0x8007 006CSSDR == SSP Data Register
0x8007 006CSSP Transmit 0x81C01B 1110
0x8007 006CSSP Receive 0x81C01B 1111
0x8007 0070Reserved
0x8007 0074SSSR == SSP Status Register
0x8007 0078..0x8007 FFFFReserved
0x9000 0000System Control Module Registers256 MB
OS Timer Register Locations
0x9000 0000OSMR[0] == OS Timer Match Registers[3:0]
0x9000 0004OSMR[1]
0x9000 0008OSMR[2]
0x9000 000COSMR[3]
0x9000 0010OSCR == OS Timer Counter Register
0x9000 0014OSSR == OS Timer Status Register
0x9000 0018OWER == OS Timer Watchdog Enable Register
0x9000 001COIER == OS Timer Interrupt Enable Register
Real Time Clock Register Locations
0x9001 0004RCNR == RTC Count Register
0x9001 0000RTAR == RTC Alarm Register
0x9001 0010RTSR == RTC Status Register
0x9001 0008RTTR == RTC Timer Trim Register
Power Manager Register Locations
0x9002 0000PMCR == Power Manager Control Register
0x9002 0004PSSR == Power Manager Sleep Status Register
0x9002 0008PSPR == Power Manager Scratch Pad Register
0x9002 000CPWER == Power Manager Wakeup Enable Register
0x9002 0010PCFR == Power Manager General Configuration Register
0x9002 0014PPCR == Power Manager PLL Configuration Register
0x9002 0018PGSR == Power Manager GPIO Sleep State Register
0x9002 001CPOSR == Power Manager Oscillator Status Register
Reset Controller Register Locations
0x9003 0000RSRR == Reset Controller Software Reset Register
0x9003 0004RCSR == Reset Controller Status Register
0x9003 0008TUCR == Reserved for Test
GPIO registers
0x9004 0000GPLR == GPIO Pin Level Register
0x9004 0004GPDR == GPIO Pin Direction Register
0x9004 0008GPSR == GPIO Pin Output Set Register
0x9004 000CGPCR == GPIO Pin Output Clear Register
0x9004 0010GRER == GPIO Rising-Edge Detect Register
0x9004 0014GFER == GPIO Falling-Edge Detect Register
0x9004 0018GEDR == GPIO Edge Detect Status Register
0x9004 001CGAFR == GPIO Alternate Function Register
Interrupt Controller Registers
0x9005 0000ICIP == Interrupt Controller IRQ Pending Register
0x9005 0004ICMR == Interrupt Controller Mask Register
0x9005 0008ICLR == Interrupt Controller Level Register
0x9005 0010ICFP == Interrupt Controller FIQ Pending Register
0x9005 0020ICPR == Interrupt Controller Pending Register
0x9005 000CICCR == Interrupt Controller Control Register
0x9006 0000Peripheral Pin Controller (PPC)
0x9006 0000PPDR == PPC Pin Direction Register
0x9006 0004PPSR == PPC Pin State Register
0x9006 0008PPAR == PPC Pin Assignment Register
0x9006 000CPSDR == PPC Sleep Mode Pin Direction Register
0x9006 0010PPFR == PPC Pin Flag Register
0x9006 0014..0x9006 FFFFReserved (but for the two addresses below)
0x9006 0028HSCR2 == HSSP Control Register 2
0x9006 0030MCCR1 == MCP Control Register 1
0x9006 0034..0x9006 FFFFReserved
0xA000 0000Memory and Expansion Registers256 MB
0xA000 0000MDCNFG == DRAM Configuration Register
0xA000 0004MDCAS0 == DRAM CAS Waveform Shift Register 0
0xA000 0008MDCAS1 == DRAM CAS Waveform Shift Register 1
0xA000 000CMDCAS2 == DRAM CAS Waveform Shift Register 2
0xA000 0010MSC0 == Static Memory Control Register 0
0xA000 0014MSC1 == Static Memory Control Register 1
0xA000 0018MECR == Expansion Bus Configuration Register
0xB000 0000LCD and DMA Registers256 MB
DMA Register List
Channel 0 Registers
0xB000 0000DDAR0 == DMA Device Address Register
0xB000 0004DCSR0 == DMA Control/Status Register 0 - write ones to set
0xB000 0008write ones to clear
0xB000 000Cread only
0xB000 0010DBSA0 == DMA Buffer A Start Address 0
0xB000 0014DBTA0 == DMA Buffer A Transfer Count 0
0xB000 0018DBSB0 == DMA Buffer B Start Address 0
0xB000 001CDBTB0 == DMA Buffer B Transfer Count 0
Channel 1 Registers
0xB000 0020DDAR1 == DMA Device Address Register 1
0xB000 0024DCSR1 == DMA Control/Status Register 1 - write ones to set
0xB000 0028write ones to clear
0xB000 002Cread only
0xB000 0030DBSA1 == DMA Buffer A Start Address 1
0xB000 0034DBTA1 == DMA Buffer A Transfer Count 1
0xB000 0038DBSB1 == DMA Buffer B Start Address 1
0xB000 003CDBTB1 == DMA Buffer B Transfer Count 1
Channel 2 Registers
0xB000 0040DDAR2 == DMA Device Address Register 2
0xB000 0044DCSR2 == DMA Control/Status Register 2 - write ones to set
0xB000 0048write ones to clear
0xB000 004Cread only
0xB000 0050DBSA2 == DMA Buffer A Start Address 2
0xB000 0054DBTA2 == DMA Buffer A Transfer Count 2
0xB000 0058DBSB2 == DMA Buffer B Start Address 2
0xB000 005CDBTB2 == DMA Buffer B Transfer Count 2
Channel 3 Registers
0xB000 0060DDAR3 == DMA Device Address Register 3
0xB000 0064DCSR3 == DMA Control/Status Register 3 - write ones to set
0xB000 0068write ones to clear
0xB000 006Cread only
0xB000 0070DBSA3 == DMA Buffer A Start Address 3
0xB000 0074DBTA3 == DMA Buffer A Transfer Count 3
0xB000 0078DBSB3 == DMA Buffer B Start Address 3
0xB000 007CDBTB3 == DMA Buffer B Transfer Count 3
Channel 4 Registers
0xB000 0080DDAR4 == DMA Device Address Register 4
0xB000 0084DCSR4 == DMA Control/Status Register 4 - write ones to set
0xB000 0088write ones to clear
0xB000 008Cread only
0xB000 0090DBSA4 == DMA Buffer A Start Address 4
0xB000 0094DBTA4 == DMA Buffer A Transfer Count 4
0xB000 0098DBSB4 == DMA Buffer B Start Address 4
0xB000 009CDBTB4 == DMA Buffer B Transfer Count 4
Channel 5 Registers
0xB000 00A0DDAR5 == DMA Device Address Register 5
0xB000 00A4DCSR5 == DMA Control/Status Register 5 - write ones to set
0xB000 00A8write ones to clear
0xB000 00ACread only
0xB000 00B0DBSA5 == DMA Buffer A Start Address 5
0xB000 00B4DBTA5 == DMA Buffer A Transfer Count 5
0xB000 00B8DBSB5 == DMA Buffer B Start Address 5
0xB000 00BCDBTB5 == DMA Buffer B Transfer Count 5
LCD Controller
0xB010 0000LCCR0 == LCD Control Register 0
0xB010 0004LCSR == LCD Status Register
0xB010 0008..0xB010 000CReserved
0xB010 0010DBAR1 == DMA Channel 1 Base Address Register
0xB010 0014DCAR1 == DMA Channel 1 Current Address Register
0xB010 0018DBAR2 == DMA Channel 2 Base Address Register
0xB010 001CDCAR2 == DMA Channel 2 Current Address Register
0xB010 0020LCCR == LCD Controller Control Register 1
0xB010 0024LCCR2 == LCD Controller Control Register 2
0xB010 0028LCCR3 == LCD Controller Control Register 3
0xB010 002C..0xB010 FFFFReserved
0xBFFF FFFF
0xC000 0000Dynamic Memory - DRAM
0xC000 0000DRAM Bank 0128 Mbyteunused
0xC800 0000DRAM Bank 1128 Mbyteunused
0xD000 0000DRAM Bank 2128 Mbyteunused
0xD800 0000DRAM Bank 3128 Mbyteunused
0xE000 0000Zeros Bank128 MbyteCache Flush replacement data.
Reads return Zero.
0xE800 0000..0xFFFF FFFFReserved384 MBAccessing this space causes a Data Abort Exception.
Gerald Q. Maguire Jr.
Last modified: Mon Apr 20 12:51:18 EDT