[1]
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R. Jordão, F. Bahrami, R. Chen, and I. Sander.
A multi-view and programming language agnostic framework for
model-driven-engineering.
In Forum on Specification & Design Languages 2022, Linz,
Sept. 2022.
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[2]
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I. Sander, I. Söderquist, M. Ekman, R. Jordão, F. Bahrami, R. Chen, and
A. Åhlander.
Towards correct-by-construction design of safety-critical embedded
avionics systems.
In 33rd Congress of the International Council of the
Aeronautical Sciences (ICAS2022), Stockholm, Sweden, Sept. 2022.
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[3]
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C. Schwartz, I. Sander, R. Jordão, F. Bruhn, M. Persson, J. Ekblad, and
C. Fuglesang.
On-board satellite data processing to achieve smart information
collection.
In P. Schelkens and T. Kozacki, editors, Optics, Photonics and
Digital Technologies for Imaging Applications VII, volume 12138, page
121380I. International Society for Optics and Photonics, SPIE, 2022.
[ DOI |
http ]
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[1]
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S.-H. Attarzadeh-Niaki, I. Sander, and M. Ahmadi.
An automated parallel simulation flow for cyber-physical system
design.
Integration, 77:48 -- 58, Mar. 2021.
[ DOI |
http ]
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[2]
|
R. Jordão, I. Sander, and M. Becker.
Formulation of design space exploration problems by composable design
space identification.
In Design, Automation Test in Europe Conference
Exhibition (DATE), Feb. 2021.
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[3]
|
G. Ungureanu, J. de Medeiros, T. Sundström, I. Söderquist,
A. Åhlander, and I. Sander.
ForSyDe-Atom: Taming complexity in cyber physical system design
with layers.
ACM Trans. Des. Autom. Electron. Syst., 2021.
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[4]
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D. S. Loubach, R. Bonna, G. Ungureanu, I. Sander, and I. Söderquist.
Classification and mapping of model elements for designing runtime
reconfigurable systems.
IEEE Access, 9:156337--156360, 2021.
[ DOI ]
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[1]
|
K. Rosvall, T. Mohammadat, G. Ungureanu, J. Öberg, and I. Sander.
Exploring power and throughput for dataflow applications on
predictable NoC multiprocessors.
In Euromicro Conference on Digital System Design (DSD 2018),
Prague, Czech Republic, Aug. 2018.
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[2]
|
G. Ungureanu, J. de Medeiros, and I. Sander.
Bridging discrete and continuous time models with atoms.
In Design Automation and Test in Europe (DATE 2018),
Dresden, Germany, Mar. 2018.
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[3]
|
J. de Medeiros, G. Ungureanu, and I. Sander.
An algebra for modeling continuous time systems.
In Design Automation and Test in Europe (DATE 2018),
Dresden, Germany, Mar. 2018.
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[4]
|
K. Rosvall and I. Sander.
Flexible and trade-off-aware constraint-based design space
exploration for streaming applications on heterogeneous platforms.
ACM Transactions on Design Automation of Electronic Systems
(TODAES), 23(2), Jan. 2018.
[ DOI ]
|
[1]
|
S.-H. Attarzadeh-Niaki and I. Sander.
Automatic construction of models for analytic system-level design
space exploration problems.
In Design Automation and Test in Europe (DATE 2017),
Lausanne, Switzerland, Mar. 2017.
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[2]
|
G. Ungureanu and I. Sander.
A layered formal framework for modeling of cyber-physical systems.
In Design Automation and Test in Europe (DATE 2017),
Lausanne, Switzerland, Mar. 2017.
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[3]
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K. Rosvall, N. Khalilzad, G. Ungureanu, and I. Sander.
Throughput propagation in constraint-based design space exploration
for mixed-criticality systems.
In Proceedings of the 2017 Workshop on Rapid Simulation and
Performance Evaluation: Methods and Tools, RAPIDO '17, Stockholm, Sweden,
January 2017.
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[4]
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K. Grüttner, R. Görgen, S. Schreiner, F. Herrera, P. Penil, J. Medina,
E. Villar, G. Palermo, W. Fornaciari, C. Brandolese, D. Gadioli, E. Vitali,
D. Zoni, S. Bocchio, L. Ceva, P. Azzoni, M. Poncino, S. Vinco, E. Macii,
S. Cusenza, J. Favaro, R. Valencia, I. Sander, K. Rosvall, N. Khalilzad, and
D. Quaglia.
CONTREX: Design of embedded mixed-criticality CONTRol systems
under consideration of EXtra-functional properties.
Microprocessors and Microsystems: Embedded Hardware Design
(MICPRO), 2017.
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[5]
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M. Fakih, A. Lenz, M. Azkarate-Askasua, J. Coronel, A. Crespo, S. Davidmann,
J. C. D. Garcia, N. G. Romero, K. Grüttner, S. Schreiner, R. Seyyedi,
R. Obermaisser, A. Maleki, J. Öberg, M. T. Mohammadat,
J. Pérez-Cerrolaza, I. Sander, and I. Söderquist.
SAFEPOWER project: Architecture for safe and power-efficient
mixed-criticality systems.
Microprocessors and Microsystems, 52(Supplement C):89 -- 105,
2017.
[ DOI |
http ]
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[6]
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I. Sander, A. Jantsch, and S.-H. Attarzadeh-Niaki.
ForSyDe: System design using a functional language and models of
computation.
In S. Ha and J. Teich, editors, Handbook of Hardware/Software
Codesign, pages 99--140. Springer Netherlands, 2017.
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[7]
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M. Ashjaei, N. Khalilzad, S. Mubeen, M. Behnam, I. Sander, L. Almeida, and
T. Nolte.
Designing end-to-end resource reservations in predictable distributed
embedded systems.
Real-Time Systems, 53(6):916--956, Nov 2017.
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[8]
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S.-H. Attarzadeh-Niaki, E. Altinel, M. Koedam, A. Molnos, I. Sander, and
K. Goossens.
A Composable and Predictable MPSoC Design Flow for Multiple
Real-Time Applications, pages 157--174.
Springer International Publishing, Cham, 2017.
[ DOI |
http ]
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[1]
|
N. Khalilzad, K. Rosvall, and I. Sander.
A modular design space exploration framework for multiprocessor
real-time systems.
In Forum on Specification and Design Languages (FDL 2016),
Bremen, Germany, Sept. 2016.
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[2]
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R. Görgen, K. Grüttner, F. Herrera, G. Palermo, W. Fornaciari,
C. Brandolese, D. Gadioli, S. Bocchio, L. Ceva, P. Azzoni, M. Poncino,
S. Vinco, E. Macii, S. Cusenza, J. Favaro, R. Valencia, I. Sander,
K. Rosvall, D. Quaglia, P. Penil, J. Medina, and E. Villar.
CONTREX: Design of embedded mixed-criticality CONTRol systems
under consideration of EXtra-functional properties.
In Proceedings of the 19th Euromicro Conference on Digital
Systems Design (DSD 2016), Limassol, Cyprus, Sept. 2016.
[ DOI ]
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[3]
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A. Lenz, M. A.-A. Blázquez, J. Coronel, A. Crespo, S. Davidmann, J. C. D.
Garcia, N. G. Romero, K. Grüttner, R. Obermaisser, J. Öberg,
J. Perez, I. Sander, and I. Söderquist.
SAFEPOWER project: Architecture for safe and power-efficient
mixed-criticality systems.
In Proceedings of the 19th Euromicro Conference on Digital
Systems Design (DSD 2016), Limassol, Cyprus, Sept. 2016.
[ DOI ]
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[4]
|
G. H. Blindell, C. Menne, and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Synthesizing Code for GPGPUs from Abstract Formal Models,
pages 115--134.
Springer, 2016.
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[5]
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S. Attarzadeh-Niaki and I. Sander.
An extensible modeling methodology for embedded and cyber-physical
system design.
SIMULATION: Transactions of The Society for Modeling and
Simulation International, 92(8):771--794, 2016.
[ DOI ]
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[1]
|
S. Attarzadeh-Niaki and I. Sander.
Integrating functional mock-up units into a formal heterogeneous
system modeling framework.
In International Symposium on Computer Architecture and Digital
Systems (CADS), Oct. 2015.
[ DOI ]
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[2]
|
P. Diallo, S.-H. Attarzadeh-Niaki, F. Robino, I. Sander, J. Champeau, and
J. Öberg.
A formal, model-driven design flow for system simulation and
multi-core implementation.
In Symposium on Industrial Embedded Systems (SIES), Siegen,
Germany, June 2015.
[ DOI ]
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[3]
|
B. Navas, I. Sander, and J. Öberg.
Towards cognitive reconfigurable hardware: Self-aware learning in
RTR fault-tolerant SoCs.
In International Symposium on Reconfigurable
Communication-centric Systems-on-Chip (ReCoSoc), Bremen, Germany, June 2015.
[ DOI ]
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[4]
|
E. Paone, F. Robino, G. Palermo, V. Zaccaria, I. Sander, and C. Silvano.
Customization of OpenCL applications for efficient task mappings
under heterogeneous platform constraints.
In Design Automation and Test in Europe (DATE '15),
Grenoble, France, Mar. 2015.
[ DOI ]
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[5]
|
F. Herrera and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Combining Analytical and Simulation-Based Design Space
Exploration for Efficient Time-Critical and Mixed-Criticality Systems, pages
167--188.
Springer, 2015.
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[6]
|
F. Herrera, K. Rosvall, I. Sander, E. Paone, and G. Palermo.
An efficient joint analytical and simulation-based design space
exploration flow for predictable multi-core systems.
In Workshop on Rapid Simulation and Performance Evaluation:
Methods and Tools (RAPIDO), Amsterdam, The Netherlands, Jan. 2015.
[ DOI ]
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[7]
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S. H. Attarzadeh Niaki, M. Mikulcak, and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Automatic Generation of Virtual Prototypes from Platform
Templates, pages 147--166.
Springer, 2015.
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[1]
|
B. Navas, J. Öberg, and I. Sander.
On providing scalable self-healing adaptive fault-tolerance to RTR
SoCs.
In International Conference on ReConFigurable Computing and
FPGAs (ReConFig 2014), Cancun, Mexico, Dec. 2014.
[ DOI ]
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[2]
|
G. H. Blindell, C. Menne, and I. Sander.
Synthesizing code for GPGPUs from abstract formal models.
In Forum on Specification and Design Languages (FDL 2014),
Munich, Germany, Oct. 2014.
[ DOI ]
|
[3]
|
F. Herrera and I. Sander.
An extensible infrastructure for modeling and time analysis of
predictable embedded systems.
In Forum on Specification and Design Languages (FDL 2014),
Munich, Germany, Oct. 2014.
[ DOI ]
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[4]
|
B. Navas, J. Öberg, and I. Sander.
The upset-fault-observer: A concept for self-healing adaptive fault
tolerance.
In NASA/ESA Conference on Adaptive Hardware and Systems,
Leicester, UK, July 2014.
[ DOI ]
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[5]
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K. Rosvall and I. Sander.
A constraint-based design space exploration framework for real-time
applications on MPSoCs.
In Design Automation and Test in Europe (DATE '14),
Dresden, Germany, Mar. 2014.
[ DOI ]
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[1]
|
B. Navas, J. Öberg, and I. Sander.
Towards the generic reconfigurable accelerator: Algorithm
development, core design, and performance analysis.
In International Conference on ReConFigurable Computing and
FPGAs (ReConFig 2013), Cancun, Mexico, Dec. 2013.
[ DOI ]
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[2]
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S. Li, N. Farahini, A. Hemani, K. Rosvall, and I. Sander.
System level synthesis of hardware for DSP applications using
pre-characterized function implementations.
In International Conference on Hardware-Software Codesign and
System Synthesis (CODES+ISSS 2013), Montreal, Canada, Oct. 2013.
[ DOI ]
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[3]
|
F. Herrera, S. H. Attarzadeh Niaki, and I. Sander.
Towards a modelling and design framework for mixed-criticality SoCs
and systems-of-systems.
In Procceedings of the 16th Digital Systems Design (DSD 2013),
Santander, Spain, Sept. 2013.
[ DOI ]
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[4]
|
S. H. Attarzadeh Niaki, M. Mikulcak, and I. Sander.
Rapid virtual prototyping of real-time systems using predictable
platform characterizations.
In Forum on Specification and Design Languages (FDL 2013),
Paris, France, Sept. 2013.
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[5]
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F. Herrera and I. Sander.
Combining analytical and simulation-based design space exploration
for time-critical systems.
In Forum on Specification and Design Languages (FDL 2013),
Paris, France, Sept. 2013.
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[6]
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G. Ungureanu, I. Reinhold, I. Sander, and W. Zapka.
Parallel software design enabling high-speed reliability testing of
inkjet printheads.
In NIP International Conference on Digital Printing
Technologies, pages 60--65, Seattle, Washington, USA, Sept. 2013.
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[7]
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S. H. Attarzadeh Niaki and I. Sander.
An automated parallel simulation flow for heterogeneous embedded
systems.
In Proceedings of Design Automation and Test in Europe
(DATE '13), pages 27--30, Grenoble, France, March 2013.
[ DOI ]
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[8]
|
B. Navas, I. Sander, and J. Öberg.
The RecoBlock SoC platform: A flexible array of reusable
run-time-reconfigurable IP-blocks.
In Proceedings of Design Automation and Test in Europe
(DATE '13), pages 833--838, Grenoble, France, Mar. 2013.
[ DOI ]
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[1]
|
J. Zhu, I. Sander, and A. Jantsch.
Performance analysis of reconfigurations in adaptive real-time
streaming applications.
ACM Transactions on Embedded Computing Systems,
11S(1):12:1--12:20, June 2012.
[ DOI |
http ]
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[2]
|
M. K. Jakobsen, J. Madsen, S. H. Attarzadeh Niaki, I. Sander, and J. Hansen.
System level modelling with open source tools.
In Embedded World, Nuremberg, Germany, February 2012.
[ .pdf ]
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[3]
|
S. H. Attarzadeh Niaki, G. S. Beserra, N. Andersen, M. Verdon, and I. Sander.
Heterogeneous system-level modeling for small and medium enterprises.
In 25th Symposium on Integrated Circuits and Systems Design
(SBCCI 2012), pages 1--6, Brasilia, Brazil, 2012.
[ DOI ]
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[4]
|
G. S. Beserra, S. H. Attarzadeh Niaki, and I. Sander.
Integrating virtual platforms into a heterogeneous MoC-based
modeling framework.
In Forum on Specification and Design Languages (FDL 2012),
pages 143--150, Vienna, Austria, 2012.
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[5]
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S. Attarzadeh Niaki, M. Jakobsen, T. Sulonen, and I. Sander.
Formal heterogeneous system modeling with SystemC.
In Forum on Specification and Design Languages (FDL 2012),
pages 160--167, Vienna, Austria, 2012.
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[1]
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J. Zhu, I. Sander, and A. Jantsch.
HetMoC: heterogeneous modelling in SystemC.
In Proceedings of Forum for Design Languages (FDL '10),
Southampton, UK, September 2010.
[ DOI ]
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[2]
|
S. Penolazzi, I. Sander, and A. Hemani.
Inferring energy and performance cost of RTOS in priority-driven
scheduling.
In Proceedings of Symposium of Industrial Embedded Systems
(SIES 2010), Trento, Italy, July 2010.
[ DOI ]
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[3]
|
J. Zhu, I. Sander, and A. Jantsch.
Pareto efficient design for reconfigurable streaming applications
on CPU/FPGAs.
In Design Automation and Test in Europe (DATE '10),
Dresden, Germany, March 2010.
[ .pdf ]
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[4]
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S. Penolazzi, I. Sander, and A. Hemani.
Predicting Energy and Performance Overhead of Real-Time
Operating Systems.
In Proceedings of Design Automation and Test in Europe
(DATE '10), Dresden, Germany, March 2010.
[ DOI ]
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[5]
|
J. Zhu, I. Sander, and A. Jantsch.
Constrained global scheduling of streaming applications on MPSoCs.
In Asia South Pacific Design Automation Conference
(ASP-DAC '10), 2010.
[ DOI ]
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[1]
|
W. H. Minhass, J. Öberg, and I. Sander.
Implementation of a scalable, globally plesiochronous locally
synchronous, off-chip NoC communication protocol.
In Proceedings of the IEEE NorChip Conference, pages 1 -- 5,
Trondheim, Norway, November 2009.
[ DOI ]
|
[2]
|
B. Navas, I. Sander, and J. Öberg.
Camera and LCM IP-cores for NIOS SOPC system.
In FPGA World, pages 18--23, Stockholm, Sweden, September
2009.
[ DOI ]
|
[3]
|
W. H. Minhass, J. Öberg, and I. Sander.
Design and implementation of a plesiochronous multi-core 4x4
network-on-chip FPGA platform with MPI HAL support.
In FPGA World, Stockholm, Sweden, September 2009.
[ DOI ]
|
[4]
|
I. Sander, J. Zhu, A. Jantsch, A. Herrholz, P. A. Hartmann, and W. Nebel.
High-level estimation and trade-off analysis for adaptive real-time
systems.
In Proceedings of the 16th Reconfigurable Architectures Workshop
(RAW 2009), pages 1--4, Rome, Italy, May 2009.
[ DOI ]
|
[5]
|
J. Zhu, I. Sander, and A. Jantsch.
Buffer minimization of real-time streaming applications on hybrid
CPU/FPGA.
In Design Automation and Test in Europe (DATE'09), pages
1506--1511, Nice, France, 2009.
[ DOI ]
|
[1]
|
J. Zhu, I. Sander, and A. Jantsch.
Performance analysis of reconfiguration in adaptive real-time
streaming applications.
In Proceedings of the 6th Workshop on Embedded Systems for
Real-Time Multimedia (ESTIMedia'08), Atlanta, USA, October 2008.
[ DOI ]
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[2]
|
J. Zhu, I. Sander, and A. Jantsch.
Energy efficient streaming applications with guaranteed throughput on
MPSoCs.
In Proceedings of the International Conference on Embedded
Software (EMSOFT'08), Atlanta, USA, October 2008.
[ DOI ]
|
[3]
|
T. Raudvere, I. Sander, and A. Jantsch.
Application and verification of local non-semantic-preserving
transformations in system design.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 27(6):1091--1103, June 2008.
[ DOI ]
|
[4]
|
I. Sander and A. Jantsch.
Modelling adaptive systems in ForSyDe.
Electronic Notes in Theoretical Computer Science (ENTCS),
200(2):39--54, 2008.
First Workshop on Verification of Adaptive Systems (VerAS 2007).
[ DOI |
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|
T. Raudvere, I. Sander, and A. Jantsch.
Synchronization after design refinements with sensitive delay
elements.
In International Conference on Hardware-Software Codesign and
System Synthesis (CODES+ISSS), Salzburg, Austria, October 2007.
[ DOI ]
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[2]
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A. Herrholz, F. Oppenheimer, P. A. Hartmann, A. Schallenberg, W. Nebel,
C. Grimm, M. Damm, J. Haase, J. Brame, F. Herrera, E. Villar, I. Sander,
A. Jantsch, A.-M. Fouilliart, and M. Martinez.
The Andres project: Analysis and design of run-time reconfigurable,
heterogeneous systems.
In International Conference on Field Programmable Logic and
Applications (FPL'07), pages 396--401, August 2007.
[ DOI ]
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[3]
|
Z. Lu, J. Sicking, I. Sander, and A. Jantsch.
Using synchronizers for refining synchronous communication onto
hardware/software architectures.
In Proceedings of the 18th IEEE/IFIP International Workshop on
Rapid System Prototyping (RSP'07), Porto Alegre, Brazil, May 2007.
[ DOI ]
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[4]
|
T. Raudvere, I. Sander, and A. Jantsch.
A synchronization algorithm for local temporal refinements in
perfectly synchronous models with nested feedback loops.
In Proceedings of the 17th Great Lakes Symposium on VLSI
(GLSVLSI '07), pages 353--358, 2007.
[ DOI ]
|
[1]
|
R. Thid, I. Sander, and A. Jantsch.
Flexible bus and NoC performance analysis with configurable
synthetic workloads.
In Proceedings of the 9th Euromicro Conference on Digital System
Design (DSD'06), Dubrovnik, Croatia, August 2006.
[ DOI ]
|
[2]
|
Z. Lu, I. Sander, and A. Jantsch.
Towards performance-oriented pattern-based refinement of synchronous
models onto NoC communication.
In Proceedings of the 9th Euromicro Conference on Digital System
Design (DSD'06), Dubrovnik, Croatia, August 2006.
[ DOI ]
|
[3]
|
Z. Lu, I. Sander, and A. Jantsch.
Refining synchronous communication onto network-on-chip best-effort
services.
In Advances in Design and Specification Languages for SoCs -
Selected Contributions from FDL 2005. Springer Verlag, April 2006.
[ DOI ]
|
[1]
|
T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch.
System level verification of digital signal processing applications
based on the polynomial abstraction technique.
In International Conference on Computer Aided Design (ICCAD
2005), November 2005.
[ DOI ]
|
[2]
|
Z. Lu, I. Sander, and A. Jantsch.
Refinement of a perfectly synchronous communication model onto
Nostrum NoC best-effort communication.
In Proceedings of the Forum on Specification and Design
Languages (FDL'05), September 2005.
[ .pdf ]
|
[3]
|
A. Jantsch and I. Sander.
Models of computation and languages for embedded system design.
IEE Proceedings on Computers and Digital Techniques,
152(2):114--129, Mar. 2005.
[ DOI ]
|
[4]
|
Z. Lu, A. Jantsch, and I. Sander.
Feasibility analysis of messages for on-chip networks using wormhole
routing.
In Proceedings of the Asia and South Pacific Design Automation
Conference, January 2005.
[ DOI ]
|
[5]
|
A. Jantsch and I. Sander.
Models of computation in the design process.
In B. M. Al-Hashimi, editor, SoC: Next Generation Electronics.
IEE, 2005.
Invited contribution.
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I. Sander, A. Jantsch, and H. Tenhunen.
The platform as interface in a SoC design curriculum.
In Proceedings of the 5th European Workshop on Microelectronics
Education, April 2004.
[ .pdf ]
|
[2]
|
T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch.
Polynomial abstraction for verification of sequentially implemented
combinational circuits.
In Design, Automation and Test in Europe Conference (DATE
2004), Paris, France, February 2004.
[ DOI ]
|
[3]
|
I. Sander and A. Jantsch.
System modeling and transformational design refinement in ForSyDe.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 23(1):17--32, January 2004.
[ DOI ]
|
[1]
|
T. Raudvere, I. Sander, A. K. Singh, and A. Jantsch.
Verification of design decisions in ForSyDe.
In Proceedings of the 1st International Conference on Hardware -
Software Codesign and System Synthesis (CODES+ISSS), Newport Beach,
California, USA, October 2003.
[ DOI ]
|
[2]
|
I. Sander, A. Jantsch, and Z. Lu.
Development and application of design transformations in ForSyDe.
IEE Proceedings - Computers & Digital Techniques,
5:313--320, September 2003.
Special Issue - Best of DATE '03.
[ DOI ]
|
[3]
|
I. Sander.
System Modeling and Design Refinement in ForSyDe.
PhD thesis, Royal Institute of Technology, Stockholm, Sweden, April
2003.
[ .pdf ]
|
[4]
|
I. Sander, A. Jantsch, and Z. Lu.
Development and application of design transformations in ForSyDe.
In Design, Automation and Test in Europe Conference (DATE
2003), pages 364--369, Munich, Germany, March 2003.
[ DOI ]
|
[1]
|
I. Sander, P. Kolodziejski, and J.-P. Leibig.
Using a digital recording machine as the main thread in a project
based electrical engineering curriculum.
In Proceedings of the 31st ASEE/IEEE Frontiers in Education
Conference (FIE 2001), volume 3, pages 14--19, Reno, Nevada, USA, October
2001.
[ DOI ]
|
[2]
|
A. Jantsch, I. Sander, and W. Wu.
The usage of stochastic processes in embedded system specifications.
In Proceedings of the Ninth International Symposium on
Hardware/Software Codesign, pages 5--10, Copenhagen, Denmark, April 2001.
[ DOI ]
|
[3]
|
A. Jantsch, S. Kumar, I. Sander, B. Svantesson, J. Öberg, A. Hemani,
P. Ellervee, and M. O'Nils.
A comparison of six languages for system level description of telecom
applications.
In J. Mermet, editor, Electronic Chips & System Design
Languages, chapter 15, pages 181--192. Kluwer Academic Publisher, 2001.
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|
I. Sander and A. Jantsch.
System synthesis utilizing a layered functional model.
In Proceedings Seventh International Workshop on
Hardware/Software Codesign, pages 136--140, Rome, Italy, May 1999. ACM
Press.
[ DOI ]
|
[2]
|
I. Sander and A. Jantsch.
System synthesis based on a formal computational model and skeletons.
In Proceedings IEEE Workshop on VLSI'99, pages 32--39,
Orlando, Florida, USA, April 1999. IEEE Computer Society.
[ DOI ]
|
[3]
|
I. Sander and A. Jantsch.
Formal system design based on the synchrony hypothesis, functional
models, and skeletons.
In Proceedings of the 12th international conference on VLSI
Design, pages 318--323, Goa, India, January 1999. IEEE Computer Society.
[ DOI ]
|