Project Overview
The NoC system Generator is a design flow, which can generate highly configurable NoC-based MPSoC for FPGA instantiation. The design flow has been developed to enable rapid HW/SW co-design and design space exploration (DSE) through emulation on FPGA. The generated multiprocessor platform connects the processors using the Nostrum NoC architecture and design methodology. The platform implements the distributed memory model and processors communicate using the provided communication primitives written in the C language, which are automatically generated by the flow and customized to provide services for the particular generated system.
The flow starts from a set of C application files and an XML configuration file. Through the XML file the user selects the target technology, NoC topology, kind of router and interconnection scheme. The flow automatically creates the multi processor implementation on the selected target FPGA, generates drivers to provide the communication primitives, and places the provided C application software on the cores specified by the user.