7.5pt advanced level
Also given as IL3002 for PhD students
CAD software and circuit simulators are indispensable tools when designing integrated circuits.
To meet today's demanding project schedules it is important to master a wide range of design tools and understand limitations of different simulation methods.
The goal of this course is to give an overview of EDA (Electronic Design Automation) tools suitable for Analog and Mixed signal circuit design, with special focus on the Cadence tool suite. The course gives understanding of different simulation algorithms and include useful tips for efficient design project management.
The course is suitable for undergraduate and PhD students working with analog and mixed signal ASIC circuit design.
No new course run is scheduled. If you are interrested attending the course, please contact fjon@kth.se.
In 2012 the course is given as a self study course with lectures on selected topics.
Written report describing simulation results and methods used in individual design project. The design are preferably related to the students PhD project.
Lecture 1
Monday April 2nd, 13:00 in the ICT conference room, Forum 7th floor, A elevator
Homework: Lab 1, Lab 2, Lab 3
Lecture 2
Monday April 16, 13:00, Darlington conference room.
DC and AC simulation theory.
Homework: Lab 4, Lab 5
Lecture 3
Thursday May 3. 9:00, Darlington conference room
Transient simulation theory.
Homework: Lab 6, 7 (Layout)
Lecture 4
Tuesday May 15
Mixed signal design
Homework: Lab 8, 9, 10 (Digital Frontend, Backend)
Lecture 5
Monday June 4
Course wrapup. Prepare for project.
April 2nd, ICT kansli conference room, Forum 7th floor, C-elevator.
CAD tools overview
Fabs and design-kits
The Unix environment
Lecture 1: Notes
Exercise 1: lab1
Schematic entry
Creating and modifying symbols
Hierarchical designs
Net names and buses
Using design variables
Customising .cdsinit
Exercise 2: lab2
Simulation of low frequency amplifiers
Basic simulation (DC, AC, Transient)
Sensitivity
Noise
Pole Zero plots
Convergence
Exercise 3: lab3
CMOS technology trends
CMOS process flow : front end (FE) and back end (BE)
Layout and Design for Manufacturing (DfM)
Passive components
Deep submicron effects and parasitics
RF and baseband models
Corner models
Active and passive components
Exercise 4: lab4
Lecture notes and Lecture slides
Integration methods
Stability
Numerical damping
Accuracy control
Exercise 5: lab5
Linearity, IP3
Simulation of weakly and strongly non-linear circuits
Periodic Steady State simulation - Shooting and HB methods
Quasi Periodic Steady State, Simulation of modulated amplifiers
Speed up techniques
Lecture notes: Lecture notes
Layout techniques
Device matching
Routing sensitive wires
Grounding
Kelvin connections
Exercise 6: lab6
DRC
LVS
Parasitic extraction
Electron migration
Metal coverage
Antenna rules
Pad rules
Die sealing
Exercise 7: lab7
Front End and Back end
Design synthesis
Place and route
Floor planning
Supply net routing
Exercise 8: lab
Behavioural models
Importing netlist and layout
Verilog-A
Compact models
Convergence and speed considerations
Using config view to control simulation
Exercise 9: lab
On chip passive components
Inductors
Modelling and optimization
Interference
Exercise 10: lab10
Preparing for tapeout
Creating GDSII files
Process options
Bond diagram
PCB board
Identification
Managing projects (revision control)
Efficient simulation techniques
Ocean scripts
Automatic documentation
Import and export from Matlab and Excel
Exercise 11: lab11 (optional)
Information about design projects is available on the projects page.