Entity name:
Architecture name:
port, number:
signal, number:
Port / Signal name:
Port direction:
IN
OUT
INOUT
BUFFER
Port / Signal type:
BIT
BIT_VECTOR
BOOLEAN (bit)
CHARACTER ( bit)
INTEGER
STD_LOGIC (bit)
STD_LOGIC_VECTOR
UNSIGNED
range from:
to:
VHDL generator Version ©1999
message box:
port:
signal: