Entity name:

Architecture name:

port, row number:

signal, row number:

Port / Signal name:

Port direction:

Port / Signal type:

range from: to:


VHDL generator Version ©1999

message box:
   
port:
1:
2:
3:
4:
5:
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7:
8:
9:
signal:
1:
2:
3:
4:
5:

-- Created with web VHDL generator.
-- Please mark code, copy and paste
-- to your VHDL file.
library IEEE;
use IEEE.std_logic_1164.all;
use work.all;
 
ENTITY IS
      PORT(









      );
END;

ARCHITECTURE OF IS



BEGIN
 
      -- Write your code here.
 
END ;