Entity name:

Architecture name:

component, row number:

Port name:

Port direction:

Port type:

range from: to:

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-- Created with web VHDL generator.
-- Please mark code, copy and paste
-- to your VHDL file.
library IEEE;
use IEEE.std_logic_1164.all;
use work.all;
 
ENTITY IS
      PORT(









      );
END;

ARCHITECTURE OF IS
-- SIGNAL
BEGIN
 
      -- Write your code here.
 
END ;