George Ungureanu

During 2013-2020 I have been a PhD Student, at KTH - Royal Institute of Technology in Stockholm, Sweden. I worked in the Division of Electronics and Embedded Systems at the School of Electrical Engineering and Computer Science.

I worked under the supervision of Ingo Sander (2013-2020), Christian Schulte (2016-2020), and Werner Zapka (2013-2015).

About my research

Research topics

My research tackles problems in the area of embedded and cyber-physical systems design. Here are a few highlights:

ForSyDe (Formal System Design) is a methodology providing modeling and refinement techniques that can be used as part of the design process of SoCs. Founded by Ingo_Sander, it has become an open-source initiative.

ForSyDe-Atom is a spin-off of the ForSyDe-Shallow DSL, with focus on: 1) orthogonalization of concerns; 2) deconstruction of semantics to their core; 3) primitive interaction.

DeSyDe is a design space exploration tool for system-level optimization of heterogeneous platforms shared by multiple applications, founded by Kathrin Rosvall.

CoInSyDe is a multi-target component-based template expander used for synthesizing compilable code from solved (e.g. mapped, scheduled) application models.

f2cc (ForSyDe-to-CUDA C) is a software synthesis tool developed as part of the ForSyDe design flow, carrying on the work of Gabriel Hjort Blindell

In partnership with Xaar I was involved in the development of an on-line reliability system for industrial printheads, having high throughput demand and real-time constraints.

Meanwhile, keen on my work, I am gathering more insight in the following topics:

Correct-by-design

Most resources spent in designing a real-time, especially safety-critical system, are spent during validation. This is why in our research group we opt for a "correct-by-construction" approach on system design

Heterogeneity

Putting different stuff together in the same system is fun, but there are chances that things blow up. Therefore we need to understand systems both as a whole and as individual units trying to understand each other.

Time domains

Combining continuous dynamics and different computing models almost always ends up in chaotic behavior. This is because different parts of a system lack a common understanding about what time actually means.

The parallel paradigm

The abrupt shift towards parallel computing has left many gaps in understanding how thing actually work. This is where us, researchers, come into the picture! [check Ch.3 of my MSc Thesis for more...]

Functional programming

This paradigm lets you describe programs as abstractions rather than as instructions. Combined with a powerful algebra of types, this is an awesome tool for system design.

Computer languages

It is a growing endeavour to make machines understand what we want them to do. In the context of EDA, I am tackling this by trying to find the minimal set of language constructs for describing and synthesizing systems.

During my studies I have been involved in the following projects:

CASTOR: Correct-by-Construction Seed project leading to a pre-study aiming to identify how formal verification techniques can be further integrated into ForSyDe.

CORRECT Swedish national project which aims to create a full correct-by-construction design flow, including design space exploration, down to software generation.

SAFEPOWER EU project whose objective is to enable the development of cross-domain mixed-criticality systems with low power, safety and security requirements.

CONTREX EU project aiming to enable energy efficient design through analysis and optimisation with regard to application demands at different criticality levels.

iPack VINN Excellence Center aspiring to advance the Swedish market for intelligent packaging by developing innovative electronics in vision of internet-of-things.

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My publications so far

  • George Ungureanu, José Edil Guimarães De Medeiros, Timmy Sundström, Ingemar Söderquist, Anders Åhlander, and Ingo Sander. "ForSyDe-Atom: Taming Complexity in Cyber Physical System Design with Layers". in ACM Transactions on Embedded Computing Systems (TECS), 2021, 20(2), 1-27. [ bib | doi | fulltext ]
  • G. Ungureanu, R. Jordão and I. Sander. "Exploiting Dataflow Models for Parallel Simulation of Discrete Timed Systems". In 2020 Forum for Specification and Design Languages (FDL), September 2020, (pp. 1-4). IEEE. [ fulltext | bib | doi ]
  • G. Ungureanu, T. Sundström, A. Åhlander, I. Sander, and I. Söderquist. "Formal Design, Co-Simulation and Validation of a Radar Signal Processing System". In 2019 Forum for Specification and Design Languages (FDL), September 2019, (pp. 1-8). IEEE. [ fulltext | bib | doi ]
  • R. Bonna, D. S. Loubach, G. Ungureanu & I. Sander. "Modeling and simulation of dynamic applications using scenario-aware dataflow". in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2019, 24(5), 1-29. [ bib | doi | url ]
  • G. Ungureanu, J. E. G. de Medeiros and I. Sander, "Bridging Discrete and Continuous Time Models with Atoms," in Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, s. 277-280.[ fulltext | bib | urn ]
  • Jose. E. G. de Medeiros, G. Ungureanu and I. Sander, "An Algebra for Modeling Continuous Time Systems," in Proceedings Of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, s. 861-864.[ fulltext | doi | bib | urn ]
  • K. Rosvall et al., ‘Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors’, in 2018 21st Euromicro Conference on Digital System Design (DSD), 2018.[ fulltext | doi | bib | urn ]
  • G. Ungureanu and I. Sander, ‘A layered formal framework for modeling of cyber-physical systems’, in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Lausanne, Switzerland, March 2017, pp. 1715–1720.[ fulltext | slides | doi | bib | urn ]
  • K. Rosvall, N. Khalilzad, G. Ungureanu, and I. Sander, ‘Throughput propagation in constraint-based design space exploration for mixed-criticality systems’, in Proceedings of the 2017 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '17, Stockholm, Sweden. ACM, January 2017.[ doi | bib ]
  • G. Ungureanu, I. Reinhold, I. Sander, and W. Zapka, ‘Parallel software design enabling high-speed reliability testing of inkjet printheads’, in Non-Impact Printing & Digital Fabrication Conference, NIP/DF '13, Seattle, WA, pp. 60-65, 2013. [ urn | bib ]
  • G. Ungureanu, T. Sundström, A. Åhlander, I. Sander, and I. Söderquist. "Design of Sensor Signal Processing with ForSyDe. Modeling, Validation and Synthesis", Technical Report 2019, KTH Royal Institute of Technology [ doi | fulltext ]
  • G. Ungureanu, "ForSyDe-Atom: User Manual", Technical Report 2018, KTH Royal Institute of Technology [ fulltext ]
  • G. Ungureanu, ‘Automatic software synthesis from high-level ForSyDe models targeting massively parallel processors’, Master's Thesis, KTH, School of Information and Communication Technology (ICT), 2013.[ urn | bib ]

I am also a teaching assistant

These are the courses where I teach:

I supervised the following theses:

MSc
  • J. Ziyuan, ‘Synthesis of GPU Programs from High-Level Models’, Dissertation, School of Electrical Engineering and Computer Science (EECS), 2018.[ urn ]
  • K. Sotiropoulos, ‘Parallel Simulation of SystemC Loosely-Timed Transaction Level Models’, Dissertation, KTH, School of Information and Communication Technology (ICT), 2017.[ urn ]
  • E. Fazzoletto, ‘Characterization of Partial and Run-Time Reconfigurable FPGAs’, Dissertation, KTH, School of Information and Communication Technology (ICT), 2016.[ urn ]
  • H. Woidt, ‘Hardware Synthesis in ForSyDe’, Dissertation, KTH, School of Information and Communication Technology (ICT), 2016. [ urn ]
BSc
  • D. Aros Banda and J. Wachsler, ‘Exploration of AirSim using C and Rust in the Context of SafetyCritical Systems’, Dissertation, 2018.[ urn ]

My contact details

Postal address:
KTH/ICT/ES
Electrum 229
SE-164 40 Kista
Sweden

Visiting address:
Electrum-Building, Kistagången 16, 3rd floor, elevator B

Phone: +46 8 790 4150
Fax: +46 8 790 4300
Email: ugeorge [at] kth [dot] se

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