Shuo Li received his Master's degree from KTH in 2007 and is currently a Ph.D Candidate in Department of Electronics and Embedded Systems (ESY) under Prof. Ahmed Hemani's supervision. His PhD thesis topic is "System-Level Synthesis Architectural Synthesis Framework - SYLVA". He is responsible for the tool development. Currently, he is finalizing the System Level Architectural Synthesis ( SYLVA ) framework. SYLVA is capable for multiprocessor software compilation and ASIC/FPGA/Coarse-Grained Reconfigurable Architecture synthesis.
He is also highly connected with Beijing Union University and Beijing Jiaotong University in China for the Network-on-Chip and System-on-Chip design researches.
In 2007, he did his master's thesis, "Embedded Compression Algorithm in C for Alpha RGB Graphics Content", in NXP Research, Eindhoven, the Netherlands. His job was to improve the existing algorithm and implement the improved algorithm in C. The latter version is then got patented and commercialized.
In 2005, he did his master's thesis, "8-Bit ATmega103L Compatible Micro-Controller Design in VHDL" in IMEC, Leuven, Belgium. His RTL design is then typed out in IMEC for the use in wireless sensors.
System Level Architectural Synthesis Framework (SYLVA) for ASIC, FPGA and Coarse-Grained Reconfigurable Architecture - Sole Designer
WCDMA Physical Layer in SIMULINK and
Configware - Co-Designer
A joint project between KTH and Huawei research in Beijing, China
Distributed Embedded RTOS for Intel 8051 Compatible Micro-Controller in NoC Architecture - Co-Designer
Hierarchical Compiler and Application SDK for DRRA - Co-Designer
Application Mapping and Scheduling on DRRA Using Constraint Programming - Sole Designer
DRRA Emulator and Circuit Switching Based NoC Architecture Simulator in C# - Sole Designer
Embedded Video Compression Algorithm for Graphic Content - Sole Designer
Master's thesis project in NXP semiconductors, the Netherlands
This algorithm was designed for NXP HDTV solutions and Joost.com
Website of a World of Warcraft Guild http://dios.zcold.me/ (currently, an inactivated guild) - Sole Designer
An Add-On for World of Warcraft Guild Members to Easily Spend Their DKP - Sole Designer
It is an event and schedule based Lua application.
Hardware Design Tools
RTL Compiler, SoC Encounter, C-to-Sillicon Compiler from Cadence
ModelSim from Mentor Graphics
Design Compiler from Synopsys
Quartus II from Altera
ISE Design Suite and Vivado Design Suite from Xilinx
C/C++, C#, Java, Python
Scripts, BASH in Linux and BATCH in Windows
Lua for World of Warcraft Add-Ons
EDA Tools Design
Visual Basic for Applications (VBA) in Microsoft Excel
Digital Design and Verification
CSS3 and LESS
English (Full Professional Proficiency)
Doctor of Philosophy will be awarded from Royal Institute of Technology (KTH) , Stockholm, Sweden
Topic: Hierarchical Compilation for Coarse-Grained Reconfigurable Architecture
Master of Science was awarded from Royal Institute of Technology (KTH) , Stockholm, Sweden
Major: System-on-Chip Design
Master of Science in Engineering was awarded from Groep T Internationale Hogeschool , Leuven, Belgium
Major: Design Technology
Bachelor of Science was awarded from Beijing Jiaotong University , Beijing, China
Major: Telecommunication Engineering
PhD Li Li, System Designer, Ericsson AB, Kista, Sweden
Tel: +46 (0) 10 712 2015 (office and mobile) Email: firstname.lastname@example.org
Professor Ahmed Hemani, School of ICT, KTH, Kista, Sweden
Tel: +46 (0) 8 790 4469 (office and mobile) Email: email@example.com
I am a fast learner who always think analytically. I also love to share my findings with others and learn from others. My personality makes me work efficiently and effectively no matter I am doing it solely or in a team. For instance, implementing my hardware synthesis tool and the project with Huawei cannot be successful without my independent contribution and our excellent teamwork.