Dept. of Electronic Systems
Postal address: ESY/ICT/KTH, Electrum 229, SE-164 40, Kista, Sweden
Visiting Address: 3rd Floor, Elevator B, Electrum 229, Isafjördsgatan 20-26, Kista, Sweden
Phone: +46 8 790 44 69, +46 8 790 41 03
Mobile: +46 70 727 44 69
Fax: +46 8 751 17 93
Email: hemani at kth.se
· Digital Design Using HDL (IL2217) – Since Sept. 2009. Role: Examiner
· Embedded Hardware Design in ASICs and FPGAs (IL2225) – Since Nov. 2009. Role: Lecturer and Examiner
· System Level Validation (IL2450) – Since Apr. 2010. Role: Lecturer and Examiner
Recent and Ongoing Research Projects and some key publications
Functional Untimed System Level Energy and Performance Estimation Methodology
1. S. Penolazzi, I. Sander and A. Hemani, "Estimating Bus Contention Effects on Energy and Performance in Multi-Processor SoCs". In Proceedings of Design Automation and Test in Europe (DATE’11), Grenoble, France, 2011.
2. S. Penolazzi, I. Sander and A. Hemani, "Predicting Energy and Performance Overhead of Real-Time Operating Systems". In Proceedings of Design, Automation and Test in Europe (DATE’10), Dresden, Germany, 2010, pp. 15-20.
3. S. Penolazzi, L. Bolognino and A. Hemani, "Energy and Performance Model of a SPARC Leon3 Processor". In Proceedings of the 12th Euromicro Conference on Digital System Design (DSD’09), Patras, Greece, 2009, pp. 651-656.
4. S. Penolazzi, A. Hemani and L. Bolognino, "A General Approach to High-Level Energy and Performance Estimation in SoCs". In Journal of Low Power Electronics (JOLPE’09), Volume 5, Number 3, October 2009, pp. 373-384.
5. S. Penolazzi, M. Badawi, and A. Hemani, "A Step Beyond TLM: Inferring Architectural Transactions at Functional Untimed Level". In Proceedings of VLSI-SoC Conference (VLSI-SoC’08), Rhodes, Greece, 2008, pp. 505-509.
Clocking – GALS/GRLS and dynamic distributed power management scheme
1. Ahmed Hemani, Thomas Meincke, Shashi Kumar, Peeter Ellervee, Johnny Oberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist. Lowering power consumption in clock by using Globally Asynchronous, Locally Synchronous Design Style., DAC ’99, June 21-25, 1999, New Orleans, USA
2. Jean-Michel Chabloz and Ahmed Hemani. A GALS Network-on-Chip based on Rationally-Related Frequencies. ICCD October 2011
3. Jean-Michel Chabloz, Ahmed Hemani Chapter 3: Power Management Architectures in McNOC. Chapter in the book “Scalable Multi-Core Architectures” Edited by Prof. Axel Jantsch and Prof. Dimitrios Soudris. Springer. ISBN 978-1-4419-6777-0. e-ISBN 978-1-4419-6778-7.
4. Chabloz Jean-Michel, Hemani Ahmed, Low-Latency Maximal-Throughput Communication Interfaces for Rationally-Related Clock Domains. IEEE TVLSI 2013.
Coarse Grain Reconfigurable Architecture
a. Dynamically Reconfigurable Resource Array
1. Muhammed Ali Shami, Ahmed Hemani. Partially Reconfigurable Interconnection Network for Dynamically Reprogrammable Resource Array in IEEE 8th International Conference on ASIC, October 20-23, 2009.
2. Muhammed Ali Shami, Ahmed Hemani. Control Scheme in a Coarse Grain Reconfigurable Architecture. 22nd Intl Symposium on Computer Architecture and High Performance Computing, Brasil Oct. 27-30 2010.
3. Farahini, N.; Shuo Li; Tajammul, M.A.; Shami, M.A.; Guo Chen; Hemani, A.; Wei Ye, "39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation," Circuits and Systems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.1448,1451, 19-23 May 2013
4. Nasim Farahini, Ahmed Hemani, Hassan Sohofi, Seyed M. A. H. Jafri, Muhamamd Adeel Tajammul, Kolin Paul, "Parallel Distributed Scalable Address Generation Scheme for a Coarse Grain Reconfigurable Computation and Storage Fabric," Microprocessors and Microsystems Journal, Elsevier, Nov. 2014.
b. Distributed Memory Architecture
1. Tajammul Muhammad Adeel, Shami Muhammad Ali, Hemani Ahmed. Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture, Embedded Multicore Socs (MCSoC), 2012 IEEE 6th International Symposium on, 67-74
c. Power Management and Adaptive Reconfiguration
1. Jafri, S.M.A.H.; Tajammul, M.A.; Hemani, A.; Paul, K.; Plosila, J.; Tenhunen, H., "Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs," Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on , vol., no., pp.104,112, 15-18 July 2013
Design Methods for massively parallel architectures
a. A parametric, user guided, high-level synthesis tool for CGRA
1. Omer Malik, Ahmed Hemani. “A Library Development Framework for a Coarse Grain Reconfigurable Architecture”. VLSI Design, Chennai. India. 2011.
2. Omer Malik; Ahmed Hemani, "A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture," Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on , vol., no., pp.1,6, Aug. 30 2012-Sept. 2 2012
b. SYLVA – A system level architectural synthesis tool
1. Shuo Li; Hemani, A., "Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework," Digital System Design (DSD), 2013 Euromicro Conference on , vol., no., pp.11,17, 4-6 Sept. 2013
2. Shuo Li; Farahini, N.; Hemani, A.; Rosvall, K.; Sander, I., "System level synthesis of hardware for DSP applications using pre-characterized function implementations," Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013 International Conference on , vol., no., pp.1,10, Sept. 29 2013-Oct. 4 2013
c. SiLago – A grid based large grained physical design target as a replacement for standard cells and enable high-level and system-level synthesis
1. Nasim Farahini, Ahmed Hemani, Hassan Sohofi, Li Shuo., Physical Design Aware System Level Synthesis of Hardware. SAMOX XV, June 2015, Samos Greece.
Custom Supercomputer for Brain Simulation
1. Lansner, A.; Hemani, A.; Farahini, N., "Spiking brain models: Computation, memory and communication constraints for custom hardware implementation," Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific , vol., no., pp.556,562, 20-23 Jan. 2014
2. Farahini, N.; Hemani, A.; Lansner, A.; Clermidy, F.; Svensson, C., "A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain," Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific , vol., no., pp.578,585, 20-23 Jan. 2014
Custom Supercomputer for Bioinformatics
1. Pei Liu and Ahmed Hemani, “Coarse Grain Reconfigurable Architecture for Sequence Alignment Problems in Bio-informatics”, SASP June 13-14 2010, Anahein USA
2. Pei Liu, Ahmed Hemani and Kolin Paul, “A Reconfigurable Processor for Phylogenetic Inference,” in 24th International Conference on VLSI Design (VLSI Design), 2011.
3. Pei Liu; Ebrahim, F.O.; Hemani, A.; Paul, K.; , "A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics," Reconfigurable Computing and FPGAs (ReConFig), 2011
4. Pei Liu; Hemani, A.; Paul, K., "Improved Bioinformatics Processing Unit for Multiple Applications," Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International , vol., no., pp.390,396, 21-25 May 2012
Efficient generation of high tail accuracy gaussian random numbers and Filtered Gaussian Noise Wireless Channel Models
1. Jamshaid Sarwar Malik, A Hemani, JN Malik, B Silmane, ND Gohar. Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI. IEEE Transactions on VLSI, 13th June 3014. Issue 99.
Other Key Publications
1. A Hemani, A Jantsch, S Kumar, A Postula, J Oberg, M Millberg. "NETWORK on chip: An architecture for billion transistor era". Proceeding of the IEEE NorChip Conference, 2000.
2. Ahmed Hemani; Charting the EDA roadmap. IEEE Circuits and Devices, December 2004.
3. Hemani, A; Postula, A. Self-Organization Maps in computer aided design of electronic circuits. Kohonen Maps. Edited by Erkki Oja and Samuel Kaski. Elseivier.
4. Hemani, A, Klapproth, P. Trends in SOC Architectures. Chapter in the book “Radio Design in Nanonmeter Technologies” Edited by Professor Mohammed Ismail and Delia Gonzales. Published by Springer Verlag in Summer 2006.